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Intrinsic device variability has become a significant problem in deep sub-micron technology nodes. The stochastic variations in device performance, which are a result of structural irregularities at the atomic scale, can impact both the yield and reliability of a circuit design. In this paper we describe a novel multi-reconfigurable FPGA architecture, the programmable analogue and digital array (PAnDA),...
Network on chip is a new trend in multi-core applications. Typically multiprocessor requires several Intellectual property (IP) cores based on the application needs. When the number of processing elements (PEs) increases in the multi-core device then a couple of problems encountered like traffic congestion, deadlock, interconnection problems, area, power latency and so on. There are several types...
Network on chip is a new trend in multicore applications. Typically multiprocessor requires several Intellectual property (IP) cores based on the application needs. When the number of processing elements (PEs) increases in the multi-core device then a couple of problems encountered like traffic congestion, deadlock, interconnection problems, area, power latency and so on. There are several types of...
Being a critical highway between FPGA core IPs, the routing fabric components play an integral part in overall core performance. Optimizing the components in the routing fabric region is not a trivial task when considering the multitude of variable physical parameters involved especially the profound association with software programming and constantly changing process parameters. Common optimization...
Geiselmann and Steinwandt proposed an ASIC based hardware design “YASD” for the sieving step in the number field sieve (NFS) method of integer factorization in 2004. The design is attractive since its regular structure seems suitable for implementation, however, performance valuation for 1024-bit integers has not been provided. This paper firstly evaluates the performance of YASD for 1024-bit integers...
In this paper, aiming toward a compact high-throughput reconfigurable architecture, we propose the reconfigurable processor DS-HIE. In order to achieve the characteristics of compactness and high-throughput, the DS-HIE architecture executes operations following a bit-serial computation scheme and adopts a Benes network as its routing resource. Implementing bit-serial computation brings the advantage...
Field programmable gate arrays (FPGAs) are getting more and more attractive for military and aerospace applications, among others devices. The usage of non volatile FPGAs, like Flash-based ones, reduces permanent radiation effects but transient faults are still a concern. In this paper we propose a new methodology for effectively measuring the width of radiation-induced transient faults thus allowing...
This paper describes a design flow for the circuit-level optimization of a technology. The concurrent exploration of device characteristics and library design choices leads to a more application-optimal technology. We illustrate the design flow by: 1) analyzing the impact of buffer cell design, and 2) by optimizing a 130 nm technology for low operational power.
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13-mum CMOS process. For input frequency of 25 MHz, the measured jitter is 2.46 ps (rms) and plusmn9.33 ps (pk-pk) at 200-MHz output frequency, while achievable maximum static...
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