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This paper highlights the interest of FD-SOI with high-k and metal gate as a possible candidate for low power multimedia technology. The possibility of multi-VT by combining UTBOX with back plane, back biasing, variable TiN thickness and Al2O3 in the gate stack is demonstrated. The viability of these approaches is corroborated via mobility and reliability measurements. Dual gate oxide co-integrated...
In this work, fabrication of TSNWFET on SOI with down to 25-nm TiN surrounding gate and 8-nm silicon nanowires is reported with high manufacturability and improved device reliability including reduced junction and gate leakage currents by fully eliminating the bottom parasitic channel existing in previous TSNWFET on bulk Si. And high performance is also obtained to be 1124muA/mum and 1468muA/mum at...
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
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