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Low power design is gaining prominence due to the increasing need of battery operated portable devices with high computing capability. It is the critical issue in ASIC design, as featured size is scaled down. The reliability of integrated circuit depends on the heat dissipated in the circuit. A large fraction of the power consumed is due to the clock distribution network and the high switching activity...
Quasi-Delay insensitive (QDI) circuits are the most robust and practical that can be built and are resilient to process, temperature and voltage (PVT) variations. Although there are many research papers that can translate synchronous designs into asynchronous sequential designs, to the best of our knowledge, there is neither QDI finite state machine (FSM) models proposed nor algorithms or tools designed...
With the increasing complexity of integrated circuits and transition to Systems-on-Chip (SoC) paradigm, Automatic Test pattern Generation (ATPG) becomes a crucial tool in the Electronic Design Automation (EDA) domain. ATPG based on Boolean Satisfiability (SAT) has been proposed as an alternative to classical structural algorithms for generating test patterns for single stuck-at faults in combinational...
In this paper, we present an approach to constrained automatic test pattern generation (ATPG) for functional circuits at register-transfer level (RTL) with the help of a design-for-testability (DFT) technique called F-scan. The DFT method optimally utilizes existing functional elements and paths for test, thus it effectively reduces the hardware overhead due to test. This is done by arranging all...
For ultra-low-power multimedia mobile processor (MMP) design, clock-power reduction is critical because the largest portion of the total power (more than 60% in the processor designs used in this paper) is consumed in the sequential logic. Currently, for the clock-power reduction, traditional combinational clock gating scheme has been used in industry and recently, sequential clock gating method is...
This paper presents hardware implementations of a DES cryptoprocessor with masking countermeasures and their evaluation against side-channel attacks (SCAs) in FPGAs. The masking protection has been mainly studied from a theoretical viewpoint without any thorough test in a noisy real world designs. In this study the masking countermeasure is tested with first-order and higher-order SCAs on a fully-fledged...
DLSim, a GUI-based digital logic simulation program developed by Richard Salter at Oberlin College, has been used for class demonstrations and homework exercises in the Computer Organization course at Oberlin for over ten years. Until recently its use has been limited to the component of the course dealing with low-level logic design using gates and flip-flops. A new version, DLSim 3, extends those...
Design of sequential circuits involves memory elements and combinational gates. The specification of these circuits is usually done by using the finite state machines. A microprocessor can be visualized as a large finite state machine. Thus it is a known fact that FSM design plays major role in specifying the sequential circuits. A reversible design of the infamous MIPS multi-cycle FSM is introduced...
In this paper, we propose a RT level power reduction scheme which can be used for any applications that have power problem when designers use traditional design flow. A novel wasting-toggle-rate based clock power reduction technique is introduced and verified along with traditional design flow. The proposed technique can choose optimal clock-gating style selectively to minimize the power based on...
A new approach to look-up-table (LUT) implementation for memory-based multiplication is presented, where the memory-size is reduced to half at the cost of some increase in combinational circuit complexity. The proposed design offers a saving of nearly 42% area and 38% area-delay product (ADP) at the cost of 6% increase in computational delay for memory-based multiplication of 8-bit inputs with 16-bit...
State elements are increasingly vulnerable to soft errors due to their decreasing size, and the fact that latched errors cannot be completely eliminated by electrical or timing masking. Most prior methods of reducing the soft error rate (SER) involve combinational redesign, which tends to add area and decrease testability, the latter a concern due to the prevalence of manufacturing defects. Our work...
The method of synthesis and implementation of Mealy FSMs into FPGAs is proposed. Synthesis is based on the architectural decomposition and multiple encoding of internal states. States are divided into subsets based on a current state and encoded separately in each subset. The state is decoded in the second-level circuit based on the multiple code and the code of a current state. It leads to implementation...
Higher operating frequencies may be obtained in digital systems by using wave-pipelining which permits clock frequencies higher that dictated by largest propagation delay between input and output. This, however, requires proper selection of clock periods and clock skews so as to latch the output of combinational logic circuits at the stable periods. In the literature, only trial and error and manual...
We propose a concurrent error detection (CED) scheme for a network of combinational logic blocks implemented with memory embedded in FPGAs. The proposed scheme is proven to detect - without latency - any permanent or transient fault associated with a single input or output of any component of the network. The experimental results show that the overhead for the presented CED technique is low (23.9%...
Majority voting is a commonly used approach to increase system reliability. Standard triple-module-redundancy (TMR) methods are frequently used in space applications. Using these methods, triple modules and voting circuits are implemented onto an application specific integrated circuit (ASIC) or an FPGA. When a single event upset occurs, the voting circuit neglects the failure value of a module receiving...
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