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In the implementation of spiking neuron models, which can achieve realistic neuron operation, generation of post-synaptic potentials (PSPs) is an essential function. We have already proposed a new nanodisk array structure for generating PSPs using delay in electron hopping among nanodisks. Generated PSPs have fluctuation caused by stochastic electron movement. Noise or fluctuation is effectively used...
In this paper, we propose a novel low-stress technique on-panel display gate driver. In the past, our group proposed the gate driver consists of dual pull-down, anti-fluctuating, flash pull-down transistor and low driving voltage design. This would make the circuit area too large. Therefore, we only solve the stress effect of pull down transistor. The novel circuit not only reduce 46% circuit area...
A low power and area optimized wideband variable gain amplifier (VGA) has been designed in 0.13 μm CMOS technology for an integrated Synthetic Aperture Radar (SAR) receiver. The VGA consists of three gain stages. The first stage is a resistively loaded, fixed gain source coupled pair, while the other two are variable gain degenerated differential pairs. Each stage also utilizes negative Miller capacitance...
In this paper, the reliable on-panel display gate driver is designed not only decreasing the fluctuation noise of the output signal, but also reducing the voltage stress effect of the dual pull-down transistors. The long-term high gate to source voltage causes the threshold voltage increased, and the fluctuation-noise on the output is coupled from the parasitical capacitance when the clock switches...
This paper describes a new 600V trench-gate field stop IGBT (FS-IGBT) with an advanced micro p-base (micro-P) structure in order to realize low on-state voltage drop and low Miller capacitance for the next generation 600V intelligent power module (IPM). The extra margin of the safe operating area (SOA) can be reduced by using improved over-current protection function in the IPMs, and collector-emitter...
The purpose of this paper is to present a novel technique for conducted-noise reduction in DC-DC switching regulators. In order to effectively spread the conducted-noise frequency spectrum and, at the same time, attain a satisfactory voltage regulation, two parameters (carrier frequency and pulse position) have been randomized, and the third parameter (duty ratio) has been controlled by a digital...
High precision, multiple channel, fine tunable voltage references are often required for experiments on quantum-dot devices for controlling the electron states to form specific structure. A fiber-ring based multi-channel voltage reference generator for these experiments is designed and constructed. The generator adopts 20-bit DACs and amplifiers producing high resolution voltages ranging from -10...
A clock generator for high-speed chip-to-chip link receivers was implemented in a 45-nm CMOS SOI technology. A low sensitivity to supply voltage noise was achieved by means of a low dropout voltage regulator using a replica feedback in the regulation loop, where the replica resistance is regulated by a second loop. We show that by adjusting the replica load the necessary matching of the gm/gds ratio...
SRAM cells with Vth-controllable independent double-gate (IDG) FinFETs have been successfully fabricated. The performance of the fabricated SRAM cell with various circuit topologies has been investigated comprehensively. Both a reduction of leakage current and an enhancement of read and write noise margins have been successfully demonstrated by introducing the IDG FinFETs into the SRAM cells.
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
Dependability is an important system attribute for microfluidic lab-on-chip devices. On-line testing offers a promising method for detecting defects, fluidic abnormalities, and bioassay malfunctions during chip operation. However, previous techniques for reading test outcomes and analyzing pulse sequences are cumbersome, sensitive to the calibration of capacitive sensors, and error-prone. We present...
The paper presents a detailed study on the idle leakage reduction techniques on partially depleted silicon-on-insulator (PD-SOI) CMOS SRAM. The most promising leakage reduction techniques that have been proposed are introduced, analyzed and compared into 65 nm low-power PD-SOI technology, taking into account all the SOI specific effect. Especially, it is shown that the leakage reduction techniques...
An independent-gate four-terminal FinFET SRAM have been successfully fabricated for drastic leakage current reduction. The new SRAM is consisted of a four-terminal (4T-) FinFET which has a flexible Vth controllability. The 4T-FinFET with a TiN metal gate is fabricated by a newly developed gate separation etching process. By appropriately controlling the Vth of the 4T-FinFET, we have successfully demonstrated...
In this work, the bulk-gate controlled circuit to improve the power supply ripple ratio (PSRR) of a Low Dropout Regulator (LDO) which deteriorates due to lowering power consumption is proposed. Designing with 0.25 mum CMOS process, the simulation results by HSPICE shown that the proposed circuit provides a high performance of PSRR even though 1/10 of the power consumption is reduced compare to the...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
A novel methodology for accurate and efficient static timing analysis is presented in this paper. The methodology is based on finding a frequency domain model for the gates which allows uniform treatment of the gates and interconnects. It is shown that despite the highly nonlinear overall gate model, a frequency domain model of the gate with the model parameters, gate moments, as functions of the...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
A circuit for on-chip measurement of long-term jitter, period jitter, and clock skew, is demonstrated. The circuit uses a single latch and a voltage-controlled delay element, and is evaluated in a stand-alone pad frame. Excellent reproduction of jitter measured by oscilloscope is shown. Measured jitter resolution is 1 ps or better. The circuit is also incorporated into a 2 GHz clock distribution network...
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