The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper introduces a new method of video-compress based on H.264. The coding algorithm adopts 3-D wavelet transformation and Shape Coding. In hardware implement, DSP chips and FPGA chips is adopted, FPGA completes the task of multiply clock periods operate, while DSP chips accomplishes the function of both the single clock period operate and the control of FPGA relocated calculation. Experimental...
In this paper, the architecture of a DSP/FPGA based hardware platform is presented, which is conceived to leverage programmable logic processing power for high definition video processing. The system is reconfigurable and scalable, since multiple boards may be parallelized to speed-up the most demanding tasks. JPEG 2000 and H.264, both at HD and Super HD (SHD) resolutions, have been simulated and...
Based on the group of SONY Company ICX229AK PAL image sensor chipset, PAL integrative camera with VGA interface is designed in this paper. Using the DSP + FPGA + ASIC architecture, it completes the acquisition of the video signal and display, and achieves key technologies of auto-focusing and auto iris in the FPGA. Some new type practical functions such as four images storage, mouse driver, real-time...
The essential components of future e-learning systems will include real-time video capture, video transmission, and video display; a high-definition image display at the receiver in the real-time teaching depends on the promise of a high-resolution video and a greater compression. This paper designed a high-performance terminal for the real-time video capture in e-learning systems; it is a terminal...
Digital video technology is burgeoning new standards broadening the gamut of prerequisites such as high definition video quality and more resolution substantially at lower bit rates than previous standards. Among the latest video compression algorithms, the newly established H.264 standard has become increasingly popular. However, the high coding efficiency of it comes at the cost of increase in computational...
In this paper, a color image fusion system based on DSP and FPGA is introduced. In the system, TMS320DM642 is used as the kernel processor to finish the image's fusion arithmetic, storage and display. FPGA, which has the ability to control the logic of image capturing, is used as the assistive processor. The experiment shows that this technology can obtain color fusion image.
At present, line-scan CCD camera with camera link output cannot be connected with the video ports of DM642. To this issue, based on the detailed analysis of the camera link interface protocol, three specialized chips were chose for level conversion; More over, a FIFO buffer has been designed in FPGA combined the camera specification and sequential. It solves the interface problem between camera and...
As video and image processing design challenges becoming more complex, FPGA based coprocessors are required to boost overall DSP performance. For a High Definition (HD) video compression standard like H.264/AVC, the computational performance required has outstripped what standalone DSPs can provide. This H.264/AVC standard achieves a significant improvement in coding efficiency at the cost of increased...
In this paper, we propose a novel stereoscopic video display system based on Texas Instruments (TI) company's Multimedia processor DM642. The system uses a common stereoscopic vision display method by which same scenes captured in different angles bring stereo depth information and therefore a stereoscopic perception in human's brain. The system is a time-sequential stereoscopic display system. By...
This paper presents the design of an automatic anti- collision system which composed by embedded FPGA, DSP and ARM. TMS320DM6437 DSP as the core of the system, and Spartan-3 FPGA, S3C2410 ARM9, EP1C3T144C6 FPGA is its best match. First, we designed FPGA + DSP 3 way video surveillance system and DSP + ARM + FPGA automatic warning and control system, then combined them together to complete the whole...
A programmable real-time system based on DSP and FPGA for the image object tracking is proposed. The high-performance fixed-point DSP TMS320DM643 as kernel processor is suitable for processing video signal. This paper presents in detail the work flow of the solution, the function and principle of components, such as preprocessing and OSD FPGA, the external memory interface, the transport and control...
In this article, an embedded video capturing and compressing system provided with Web intelligent based on the high speed DSP and ARM is completed. Firstly, the composition of the whole capturing and compress system is introduced; secondly, the point is that it carries out the essential technologies of data pretreatment during the video capturing and compressing, three-frame ping-pong renovating control,...
To deal with nowaday multi-standard audio and video processing, a heterogeneous multi-core SOC architecture is presented in this paper, which is composed of a general purpose RISC processor, an audio processing enhanced DSP and dedicated video processing accelerators. To exploit the task level concurrency among audio-video media decoding, an efficiency and flexible HW/SW cooperating architecture is...
This paper proposes a real-time coding system for high-resolution images. The hardware platform mainly consists of FPGA and DSP, which are grouped together in an efficient way. A fast modified SPIHT algorithm is proposed and implemented in the platform. Based on input data rate, this system can adjust the compression rate adaptively. Experimental results show that our proposed compression system meets...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.