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The HEVC is one of the most recent video coding standards, developed in order to face upcoming challenges, due to higher video quality and resolution. One of the HEVC components is the entropy encoder, which consists only of the Context Adaptive Binary Arithmetic Coding (CABAC) algorithm. The CABAC algorithm imposes some severe difficulties in order to achieve increasing throughput, due to the high...
Ultra-deep sub-micron technology is shifting the design paradigm from area optimization to power optimization. In the context of Network-on-Chip (NoC) based design, energy consumption due to data transfer among network nodes is no longer negligible. Starting from the observation that, among the two brain hemispheres around 1 out of 106 synapses are active at the same time, in this paper we propose...
High-speed serial data communication is now very popular for connecting various resources in high-performance computing systems. In such high-speed serial links, a line coding is important to control the run length (RL) and the running disparity (RD), because a large run length causes insufficient transitions on data-links that make it difficult to perform reliable clock and data recovery (CDR), and...
In this paper, a small area hardware architecture for deblocking filter of HEVC is proposed. To achieve high throughput and small area, an efficient processing order based on a CTU-based pipeline is proposed. The proposed architecture is synthesized in ALTERA Cyclone V 28nm process FPGA with 28.7K gate counts. The simulation result shows that the proposed architecture achieves an area reduction of...
This paper proposes an architecture for structured low density parity check encoder. The proposed architecture supports the limitation of input/output pins of field programmable gate array using division of information bits. The division of information bits generates latency of encoding. The proposed architecture does not store the required matrix for bit-wise multiplication and does not use cyclic...
Low Density Parity Check (LDPC) codes are a special class of error correction codes widely used in communication and disk storage systems, due to their Shannon limit approaching performance and their favorable structure. In this paper an Electronic Design Automation tool for the generation of synthesizable VHDL codes, implementing low-complexity Quasi-Cyclic LDPC (QC-LDPC) encoders is presented. The...
Low Density Parity Check (LDPC) codes are a special class of error correction codes widely used in communication and disk storage systems, due to their Shannon limit approaching performance and their favorable structure. In this paper an Electronic Design Automation tool for the generation of synthesizable VHDL codes, implementing low-complexity Quasi-Cyclic LDPC (QC-LDPC) encoders is presented. The...
This paper proposes a high throughput encoding process and encoder architecture for quasi-cyclic low-density parity-check (QC-LDPC) codes in IEEE 802.11n/ac standards. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase...
In a synchronous digital system, the activity of the clock signal is a major energy consumer. It is responsible for 15% to 45% of the total consumed energy. Once reducing the activity of the clock signal, it is possible not only a reduction of the considered energy, but also a reduction of clock skew problems and electromagnetic iteration. An interesting strategy to achieve this goal is to design...
Loss less compression algorithms are employed in a wide variety of communication- and storage-related systems. Many embedded applications, such as real-time communication log compression used in automotive systems, impose strict throughput constraints on the compression unit, creating a demand for hardware-accelerated designs. In this paper we present a modification of the Adaptive Range Coding algorithm...
The main process of the JPEG2000 is Discrete Wavelet Transform (DWT) and Embedded Block Coding with Optimized Truncation (EBCOT). MQ-Coder in the EBCOT Tier-1 is the bottleneck of the system for it is very difficult to be implemented by hardware with a high throughput. Therefore a novel architecture of MQ-Coder is proposed. Although this MQ-Coder processes only one single symbol for each clock cycle,...
This paper addresses the following base defense scenario: an Unmanned Aerial Vehicle (UAV) performs the task of perimeter alert patrol. There are m alert stations/sites located on the perimeter where a nearby breaching of the perimeter by an intruder can be sensed and is flagged by an Unattended Ground Sensor (UGS). We assume that the alert arrival process is Poisson. In order to determine whether...
A SerDes (Serializer/Deserializer) is a key component for high speed serial communication. Networks architectures and point to point communication links are vital building blocks for space-based high-speed communications and sensor data access. Honeywell has enabled optimized space communication systems with both its SerDes standard parts and its SerDes macro-cells that are part of the HX5000 Rad-Hard...
In this paper, a Johnson-encoded Reconfigurable Synchronous/Bi-Synchronous (RSBS) FIFO is proposed which can adapt its operation to either synchronous or bi-synchronous mode. The proposed FIFO which can be used to interface modules in Voltage/Frequency Islands (VFI) based Networks-on-chip, is capable of alleviating the excessive energy consumption and high performance overhead of the conventional...
Embedded block coding with optimized truncation (EBCOT) is a key algorithm in JPEG 2000 image compression system. In this algorithm, output generated by the bit plane coder (BPC) is supplied to an MQ coder. Though several high speed BPC architectures are available, overall performance EBCOT algorithm is getting restricted by the speed of an MQ coder. Therefore, we propose a high speed, area efficient...
Packet classification is an important aspect of modern network systems. Packet classification systems have traditionally been built utilizing Ternary Content Addressable Memory (TCAM) due to the high throughput needed. However, TCAMs are expensive in terms of area and power consumption. An alternative to TCAM based systems using SRAM and a novel rule encoding method has been proposed to match multiple...
Data encryption process can easily be quite complicated and usually requires significant computation time and power despite significant simplifications. This paper discusses about pipelined and non-pipelined implementation of one of the most commonly used symmetric encryption algorithm, Data Encryption Standard (DES). The platform used for this matter is, Xilinx new high performance silicon foundation,...
This paper proposes a flexible low density parity check encoder. This encoder simplifies the calculations found in other flexible encoders by increasing memory usage, allowing for parallelization and faster encoding. The flexibility of this encoder allows it to be used in emerging multi code applications and standards. To evaluate the encoder, a Verilog description was developed and synthesized on...
In this paper, we propose a new parallel-pipeline approach to design small-area low complexity convolutional encoders, suitable for high data throughput communication applications. This approach can apply both to the OTM (one to many) and the MTO (many to one) encoder schemes. Here, we will discuss the problem of designing a low cost parallel-pipeline encoder for the MTO case. The new architecture...
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