The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
We propose a novel tri-state inverter based on junction band-to-band tunneling (BTBT)-enhanced nanoscale CMOS structure. By suppressing the gate-induced drain leakage (GIDL) current, an additional stable state, “1/2”, can be generated with intermediate level from voltage dividing in series resistance of off-state n/pMOS. The high-speed performance of our proposed tri-state inverter has been estimated...
This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage platform for digital circuits compatible with bulk complementary metal–oxide–semiconductor (CMOS). Various technology options, such as gate materials, buried oxide thickness, back plane doping type, and back biasing, were investigated in order to achieve a technology platform...
Steep channel impurity-profiles formed by Si:C+Si epitaxial growth have been extensively studied. Especially in pMOS, several concerns are solved by boron-doping underneath Si:C layers. Finally, performance improvement realized by steep channel profiles has been demonstrated in both nMOS and pMOS with the same epitaxial channel structure.
The Silicon on Thin BOX (SOTB) has the smallest Vth variation among planar CMOS due to low-dose channel. This study focused on identifying the remaining components after reducing random-dopant fluctuation (RDF) by decreasing impurities in the channel. Improving short-channel-effect immunity and body-thickness uniformity is the key to further reducing the variation. An often mentioned phenomenon, larger...
This paper describes several methodologies based on a pulsed laser beam to reveal the architecture of a high integrated SDRAM, and the different classes of Single Event Effects that can occur due to cosmic radiations. At cell level, laser is used to reveal an important technological parameter: the lithography process. At memory array level, laser is a powerful tool to retrieve cell physical arrangements,...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
We have observed new charge trapping phenomena in sub-80-nm DRAM recessed- channel-array-transistor (RCAT) after Fowler-Nordheim (FN) stress. Gate stack process strongly affected the charge trapping and the trap generating in oxide bulk and interface of RCAT. According to the trapped charges and/or the generated traps after FN stress, the data retention time and writing capabilities of DRAM were dramatically...
CMOS SOI devices, realised on very thin silicon film on SIMOX material, are very attractive for ULSI application. There are many advantages over bulk that have been frequently emphasised in the literature [1]. For sub-quarter micron devices, there are several candidate architectures and device operations, depending on the gate material: - enhancement mode Partially or Fully Depleted devices, for a...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.