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After forty years of advances in integrated circuit technology, the scaling of Silicon Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has entered the nanometer dimension with the introduction of 90 nm high volume manufacturing in 2004. Presently at 45 nm going to 32 nm node in 2009, the latest technological advancement has led to low power, high-density and high-speed generation of microprocessors...
Common method for sample preparation on 45deg notch oriented <100> silicon substrate requires cleaving followed by polishing technique. To prevent surface damage during polishing, top layer capping using epoxy cover-glass is required. A faster technique named as dasiaSupermanpsila method involves only cleaving has been proposed.
Five different types of clean flux and no-clean flux, which are mainly used in flip chip die attach, have been analyzed in respect to the wettability of eutectic solder bump in flip chip PBGA. An experimental study is carried out to measure the spreading area of the eutectic solder bump processed with different types of flux. Various types of clean and no-clean flux are measured and placed on top...
In this paper a new design for conventional Partial SOI (PSOI) structure is proposed, which employs a step in buried oxide of the partial SOI structure. This new structure is called step partial buried oxide structure (SPBOS). The step in the buried oxide produces an additional electric field peak, which decreases the other electric field peaks near the drain and source junctions drastically. Our...
The silicon pillar thickness effect on vertical double gate MOSFET (VDGM) fabricated by implementing oblique rotating ion implantation (ORI) method is investigated. For this purpose, several silicon pillar thicknesses tsi were simulated. The source region was found to merge at tsi < 57 nm, forming floating body effect. The electron-hole concentration along the channel and the depletion isolation...
CDM peak currents (Ipeak) were studied for the same I/O pin on different dies and flip-chip packages. It is found that Ipeak has strong correlation with linear function of two capacitances: die-to-lid capacitance (CDUT) and CDUT normalized per die area (CDUT/A). The proposed physical model relates CDM current to the two competing discharge paths. The local path is from Si-substrate, where the charge...
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