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A non-self protection ESD scheme using grounded-gate, gate non-silicided (GG-GNS) drain/source silicide blocked (SBLK) ESD NFET offered in 45 nm SOI CMOS technology is presented based on a comprehensive study using the high current pulse characteristics. The results show that with a minimum SBLK width over drain/source, GG-GNS NFET can handle ~3.4 mA/mum current.
CDM peak currents (Ipeak) were studied for the same I/O pin on different dies and flip-chip packages. It is found that Ipeak has strong correlation with linear function of two capacitances: die-to-lid capacitance (CDUT) and CDUT normalized per die area (CDUT/A). The proposed physical model relates CDM current to the two competing discharge paths. The local path is from Si-substrate, where the charge...
The behavior of a discrete ESD protection diode during a system level ESD pulse was simulated and compared with a time resolved measurement of the real diode. The simulation results for ESD destruction level, location of the damaged zone inside the diode, and the slope of the voltage drop are very close to the measured data. Also a sudden voltage drop caused by the 2nd thermal breakdown was predicted...
We define rules to reduce the ESD test complexity for chips with large pin count. These rules exploit the structural similarity in the pad-ring and have a long history of use without bad experiences. Using these rules an automated software tool can be developed for reduced ESD test generation.
The turn-on behavior of high voltage ESD devices is studied during HBM ESD stress. Two phenomena are experimentally observed for two different HV processes and several device architectures: a voltage overshoot up to two times of the TLP triggering voltage, and a current overshoot several times the nominal HBM current.
The effect of charge injection due to CDM ESD in capacitive MEMS structures is analyzed. The results show that as feature size is reduced, ESD injected charge produces a change for the stiction effect which is inversely proportional to the square of the plate area and a change in the dielectric layer breakdown which is inversely proportional to the plate area. Charge and voltage modes in MEMS are...
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