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SRAM memory design in nanoscale regime has become increasingly challenging due to the reducing noise margins and increased sensitivity to threshold voltage variations. To overcome these challenges, different memory cells have been proposed for SRAMs with different transistor structures. These designs improve the cell stability in the subthreshold regime but suffer from bitline leakage noise, placing...
SRAM cell stability assessment is traditionally based on staticcriteria of data stability requiring three coincident points in DC butterfly curves. This definition is based on static (DC) characteristics of the cell transistors. We introduce the dynamiccriteria of cell data stability knowing that the cell operates in a dynamic environment alternating between access and non-access conditions. The...
A new SRAM circuit technique based on dynamically adjusting the wordline voltage swing is proposed in this paper for reducing the leakage power consumption and enhancing the data stability in static memory banks. With the proposed technique, the wordline voltage swing is reduced in order to suppress the voltage disturbance at the data storage nodes during a read operation. The stability of a minimum...
A new six transistor (6 T) SRAM cell with PMOS access transistors is proposed in this paper for reducing the leakage power consumption while enhancing the data stability and the integration density of FinFET memory circuits. With the proposed SRAM circuit, the voltage disturbance at the data storage nodes during a read operation is reduced by utilizing PMOS access transistors. The read stability is...
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