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Various circuit topologies and FinFET technology options for implementing brute-force latches are explored in this paper. New low-power multi-threshold voltage (multi-Vth) FinFET brute force latches based on gate-drain/source overlap engineering and independent-gate bias are proposed. Different brute-force latches are characterized and compared for active mode power consumption, propagation delay,...
A new six transistor (6 T) SRAM cell with PMOS access transistors is proposed in this paper for reducing the leakage power consumption while enhancing the data stability and the integration density of FinFET memory circuits. With the proposed SRAM circuit, the voltage disturbance at the data storage nodes during a read operation is reduced by utilizing PMOS access transistors. The read stability is...
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