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In this paper, we designed a 9T SRAM cell using dual voltage threshold (DVT) and stacking effect. To achieve high density, low power and high performance, device scaling has been continuously done that result in increase in leakage power dissipation. At sub-micron technology, about 30% of total power dissipation is due to leakage power dissipation. The purpose of this paper is to analyze the Performance...
An eight-FinFET fully differential SRAM cell is proposed in this paper to achieve stronger data stability and enhanced write ability. The p-type transistors are used for data access during read operations and transmission gates are employed to force new data into the cell during write operations. At the nominal process corner, the proposed SRAM cell enhances the read data stability, write voltage...
A seven transistor (7T) static random-access memory (SRAM) cell with single-ended read and write operations is evaluated in this paper. The cell topology consists of a single bitline, a cross-coupled inverter pair with a transmission gate employed in the feedback path, and a bitline access transistor. Simulation results with 8 Kib SRAM arrays indicate up to 49.3% reduction in leakage currents, 42...
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