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A new six transistor (6 T) SRAM cell with PMOS access transistors is proposed in this paper for reducing the leakage power consumption while enhancing the data stability and the integration density of FinFET memory circuits. With the proposed SRAM circuit, the voltage disturbance at the data storage nodes during a read operation is reduced by utilizing PMOS access transistors. The read stability is...
Data in conventional six transistor (6T) static random access memory (SRAM) cells are vulnerable to noise due to the direct coupling of data storage nodes to the bit lines during a read operation. Lowering of supply and threshold voltages leads to a significant degradation in SRAM cell stability with the scaling of CMOS technology. The SRAM cell stability is further degraded due to the process parameter...
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