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In this brief, we report on how controllable process parameters such as metal-gate physical thickness and interfacial-layer-formation method affect the electrical and structural properties of TiN/HfO2/SiO2 gate stacks. We found evidence that Hf is diffusing into chemically formed SiO2 interfacial layers during device processing. The latter is not seen when SiO2 is formed thermally. We show that the...
Experimental condition of thin SAB Oxide around 350Aring coupling with 400Aring Contact SiON film has exhibited the worst data retention behavior in One Time Programmable (OTP) & Multiple Time Programmable (MTP) memory device. Another alternative solution has been explored to improve the data retention characteristic by replacing the 400Aring silicon oxynitride (SiON) contact stopper with 300Aring...
A multi-station PECVD silicon nitride deposition process was implemented in a high volume manufacturing environment. However the occurrence of film thickness uniformity out-of-control became a chronic issue when chamber utilization was increased. Physical characterizations indicated formation of a fluoro-compound on the showerhead surface on the 1st deposition station was responsible for the failure...
A major hurdle in VLSI/ULSI technology has been the inability to grow ultrathin oxides with low defect and interface trap densities and to generate a planar stress-free silicon/silicon-dioxide (Si/SiO/sub 2/) interface. The authors describe the fabrication of thin multilayered stacked SiO/sub 2/ structure with such qualities. A huge improvement in the quality of these stacked oxides has been achieved...
Silicon oxide films less than 10-nm thick have been stressed at constant voltages from 2 V up to the breakdown voltage. The characteristics of the oxides were measured. The quasi-static C-V characteristics were used to determine the interface trap generation as a fluctuation of the stress voltage and polarity, the fluence through the oxide, and whether the stress was a DC stress or a series of pulses...
Hot-carrier effects of an n-channel LDD (lightly doped drain) MOSFET with Si/sub 3/N/sub 4//SiO/sub 2/ sidewall were investigated. As the oxide thickness under the nitride film spacer becomes thin, the initial degradation of the drain current becomes large, whereas its stress-time dependence becomes small. Moreover, relaxation of the drain current degradation in MOSFETs with only Si/sub 3/N/sub 4/...
A technique is presented for determining the thinnest oxide which satisfies a given time-dependent dielectric breakdown reliability specification. The intrinsic limit for a 10-yr lifetime at 125 degrees C is estimated to be 80 A for 5.5-V operation and 50 A for 3.6-V operation. For the particular technology studies here, 150-AA oxide meets typical reliability specifications for 5.5-V operation, and...
A model of charge transport in thermal SiO/sub 2/ with Si-implant-induced traps is proposed. In this model, traps are permitted to communicate with both the conduction band and the valence band of the Si substrate and poly-Si gate by means of direct tunneling. Electron injection in the SiO/sub 2/ conduction band, electron trapping by neutral and positively charged sites, and field depopulation of...
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