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The computing market constantly experiences the introduction of new devices, architectures, and enhancements to existing ones. Due to the number and diversity of processor and accelerator devices available, it is important to be able to objectively compare them based upon their capabilities regarding computation, I/O, power, and memory interfacing. This paper presents an extension to our existing...
Embedded computing platforms have long incorporated non-traditional architectures (e.g., FPGAs, ASICs) to combat the diminishing returns of Moore's Law as applied to traditional processors. These specialized architectures can offer higher performance potential in a smaller space, higher power efficiency, and competitive costs. A price is paid, however, in development difficulty in determining functional...
In this paper, the novel mechanical switch device: suspended-gate FET is applied to FPGA development. This device offers almost an ideal subthreshold swing and a hysteretic resistance switching, opening opportunities for low-power applications. The proposed device can be used as the building block of programmable elements and memory of an FPGA. Based on this device, the proposed FPGA architecture,...
Clock performance becomes a challenge in Structure ASIC world when system performance requirement keep increasing and logic density grows rapidly. In general, clock performance is evaluated through the clock skew and the clock integrity. The difficulty in ensuring minimum clock skew while maintaining clock integrity becomes more challenging when the device size grows and clock frequency increases...
Fault-injection experiments on Virtex-II FPGAs quantify failure and degradation modes in I/O channels incorporating triple modular redundancy (TMR). With increasing frequency (to 100 MHz), full TMR under both I/O standards investigated shows more configuration bits have a measurable performance effect.
This paper presents the performance evaluation of a PC-based active router, in terms of packet loss within the router. The architecture of the active router consists of two parts: a software part that is implemented using two Linux hosts and a hardware part that contains a PCI-based FPGA (field programmable gate array) board. A description of the modules comprising the router is given and then the...
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