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Energy efficient operation of heterogeneous networks (HetNets) has become extremely crucial owing to their fast increasing deployment. This work presents a novel approach in which an actor-critic (AC) reinforcement learning (RL) framework is used to enable traffic based ON/OFF switching of base stations (BSs) in a HetNet leading to a reduction in overall energy consumption. Further, previously estimated...
Sense amplifiers provide amplification to the very small voltage change in the memory datapath in near-zero access time. The sub-micron technology demands high performance sensing at extreme noise margins. In this paper, a state of the art latch-type storage element is proposed to provide a strong positive feedback for the small change in the differential sense input. A well synchronized 4T controlling...
The power consumption of networks has been increasing as the service over the Internet becomes popular, and has become a serious problem. Many methods to reduce the power consumption by shutting down unnecessary network devices following the environmental changes have been proposed. These methods consider only simple objectives such as the number of powered-on nodes and the maximum link utilization...
To avoid an additional large demand charge introduced by the adoption of electric vehicles (EVs), we investigate a joint energy management problem for geographically distributed data centers (DCs) and EVs of the employees in this paper. Specifically, we intend to minimize the long-term total cost of DCs and EVs by jointly scheduling DC workloads and EV charging demands, without violating heterogeneous...
This paper presents a voltage controlled ring oscillator (VCO) with a simpler temperature compensation circuit to produce a stable 4 GHz oscillation frequency. The proposed temperature compensation circuit is able to achieve a 89.25 % reduction in the variation of the center frequency of the uncompensated VCO and 108 ppm/°C temperature stability. Simulations using TSMC 0.18 µm CMOS technology show...
With the utilization of all-digital Phase locked loops (ADPLLs) in digital communication systems, the use of digitally controlled oscillators (DCO) over voltage controlled oscillators (VCO) has come into existence. In this paper, a new low power DCO structure is proposed with NMOS transistor as switching network. The DCO design is based on the CMOS inverter delay cells and ring topology. Three and...
High-speed phase frequency detector (PFD) is one of the key module for high-frequency phase locked loop (PLL) systems. The performance of PLL depends on the operation of PFD. This paper presents a new PFD design in 0.18μm CMOS technology using 3T XOR and 3T NAND gates. Supply voltage has been varied from 1.8V to 2.4V in the proposed design. The new PFD consumes power within a range from 505.78μW to...
During the design of embedded systems, many design decisions have to be made to trade off between conflicting objectives such as cost, performance, and power. Approximate computing allows to optimize each objective, yet for the sake of accuracy. This means that a functional flaw is allowed to produce an error as long as this is small enough to maintain a feasible operation of the system or guarantee...
This work compares many different transistors arrangements of XOR logic gates under PVT variability effect in 16nm device technologies: CMOS Bulk and FinFET. The objective is to identify how these two different device technologies deal with PVT variability effects on performance and power characteristics. Ten different XOR topologies are evaluated. The results show different transistor arrangements...
Achieving energy efficiency has recently become an essential aim of networking research due to the ever increasing power consumption and CO2 emissions generated by large data networks. For this problem, the emerging paradigm of Software-Defined Networks (SDN) can be seen as an attractive solution. In these networks an energy-aware routing model could be easily implemented leveraging the control and...
Mobile-edge computing (MEC) has recently emerged as a promising paradigm to liberate mobile devices from increasingly intensive computation workloads, as well as to improve the quality of computation experience. In this paper, we investigate the tradeoff between two critical but conflicting objectives in multi-user MEC systems, namely, the power consumption of mobile devices and the execution delay...
We tackle a production scheduling problem in a manufacturing system. The aim is to design an efficient exact method and find a trade-off between tardiness, storage and energy costs described by a piecewise-linear function. Therefore, we propose two time-based MILP formulations. The first one is precedence-oriented and the second is storage-oriented. These two formulations are compared and tested on...
In this paper, we construct an analytical design framework for energy efficient scheduling for delay-constrained spectrum aggregation (ESSA), where the practical hardware limitations on SA capability bring various technical challenges. Specifically, the conventional water-filling power control cannot be adopted over all the channels, and the delay-aware scheduling solution should interact with the...
In this paper, a high-speed and low-power latched comparator in a 65-nm CMOS process is presented. In our proposed structure, a latched circuit with an adjusted delayed-clock with no static power consumption is added to the conventional latch-type comparator in order to enhance the clock frequency and reduce the power consumption and the delay time. Therefore, the maximum clock frequency of our proposed...
The conventional NOR-based decoders are one ofthe fastest dynamic decoder circuits employed in microprocessors. However, they suffer from a huge amount of power dissipationresulting from the presence of short circuit paths betweenthe supply and the ground through pull-down network. Twodecoder designs with a novel selective precharge circuit have beenproposed in this paper using 32nm FinFET technology...
There is no doubt that static CMOS circuits are the best candidate for low-power and high-packing density applications. However, its performance degrades with increasing the fan-in. In this paper, a novel fast CMOS circuit that is based on a current race is presented and compared with the conventional CMOS logic from the points of view of area, power consumption, and average-time delay. The scheme...
In order to optimize the power consumption and improve the energy efficiency, the smart grid (SG) provides reliable, efficient and secured electrical power generation and distribution. Smart grid aims to manage and control the consumer demand and provide the needed power. Thus, in smart grid architecture, the information about power supply must be known, in advance, by the operator. This information...
This work explores challenges in silicon integration of scalable high-throughput “Wireless Fiber” links that exploit the increase in spatial and spectral degrees of freedom at higher carrier frequencies due to LOS MIMO spatial multiplexing and higher bandwidths. In order to utilize these increased degrees of freedom, however, hardware must scale in dynamic range, speed and number of antenna elements...
Many digital Signal processing (DSP) applications requires complex arithmetic operation which is carried by multiplier and adder units. Multiplication operation can be done as a successive addition which introduces delay in the processing. In which implementation of this technique with delay constraints leads to more challenging. Because the internal modules generate delay in propagation of processed...
A compact system for on-chip supply current wave-form reconstruction and power estimation is presented. The system, comprising a programmable current load, a sampling comparator and processing logic, is implemented in a 28nm FD-SOI system-on-chip (SoC) to monitor the supply of a digital processor generated by a switched-capacitor DC-DC converter. The monitoring system is able to reconstruct the rippling...
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