Sense amplifiers provide amplification to the very small voltage change in the memory datapath in near-zero access time. The sub-micron technology demands high performance sensing at extreme noise margins. In this paper, a state of the art latch-type storage element is proposed to provide a strong positive feedback for the small change in the differential sense input. A well synchronized 4T controlling circuit has been used to speed up the latch operation by dissipating minimal sense energy. The 13T ultra speed latch-type sense amplifier has been designed using predictive 45-nm CMOS technology and simulated in SPECTRE. The results show that the proposed design dissipates 0.152 fJ with extremely low sense time of 58.6 ps at 0.6 V. The design can function up to a supply voltage scaling of 0.4 V with an average sensing delay variation of just 29%.