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This paper concerns optical burst switching (OBS) networks with combined nodes which function as both edge and core nodes. In such architecture, we propose intermediate electronic buffering of transit burst traffic. As our simulations show, this buffering, when applied in a restricted manner, decreases the overall burst blocking probability in the network and provides better fairness among short and...
This article presents a case study and comparison of simulations carried out by SimPy 3.0 of Python module and OMNeT++ tool to explore the performance. The target of this comparison is in particular configuration of network for future steps what tools would be good to use. Two simple models of a network were created with Python and C++ language.
Existing power and rate control methods for wireless networks did not consider channel nonlinearity. This paper presents a power and rate controller for wireless networks with nonlinear channel fading. The controller is designed based on robust approach, and the performance is analyzed via linear matrix inequality (LMI). Simulation results illustrate the effectiveness of the proposed controller.
This thesis puts forward a bus signal priority assessment index system, which including bus traffic efficiency, intersection traffic efficiency, implementation difficulty factors of methods and so on. Because there are some missing, uncertain or fuzzy indices, and relevance between indices. And decision-makers would have their subjective preferences. The thesis then puts forward a bus signal priority...
Measured results are compared to simulation results for a wideband software-adjustable fast-wave line using coaxial line sections loaded with digital discrete-time non-Foster circuit elements. In the proposed approach, the negative capacitance of non-Foster circuit elements is varied by changing the signal processing in the digital non-Foster circuit. For the purposes of demonstration and comparison...
A new high-voltage-tolerant level shifter is proposed and verified in a 0.18-µm CMOS process with 1.8-V/3.3-V devices, whereas the operation voltage can be up to 12V. The output signal of high-voltage-tolerant level shifter has an offset of 3 times the normal supply voltage (VDD) of the used technology with respect to the input signal. The converting speed of level shifter is improved by using the...
Bitcoin is gaining more popularity because it is designed initially to reduce the transaction cost and improve the online payment security. It is expected to replace the traditional currencies among online transactions. Building on that, we believe that the security issues during Bitcoin payment must be put in high priority. Therefore, we performed some researches on Double-spending issues. In this...
Vehicle Ad hoc Network (VANET) is an emerging technology and a new application of mobile Ad Hoc technology in the field of traffic. As the simulation experiments cost less manpower and material resources and they are easy to reproduce the same scenario, VANET simulation technology has become a focus of scholars. But node mobility is strictly limited in the realistic traffic environment and fast moving...
Cloud computing uses internet data centers to host applications and data storage. Cloud computing resources and services are offered to customers on pay-per-use model while the quality of the offered resources and services are defined using service level agreements also known as SLAs. Unfortunately, there is no standard mechanism to verify and assure that services delivered by the cloud provider satisfy...
Controller placement is an important problem in software-defined networks. If a controller fails, there may be no controller with enough spare capacity to serve switches of the failed controller, which leads to switches being disconnected from the controller. Even if there are controllers with enough spare capacity, reassigning switches of the failed controller may drastically increase the worst case...
This paper devotes to a new 5-2 compressor designed according to a new architecture with a pure Glitchless output. A considerable increase in the speed of the operation is achieved by utilizing a new truth table, fast production of signals Cout1 and Cout2, optimum tuning of the width of the utilizing transistors, and eliminating the parasitic capacitances through merging the drain of transistors....
Named Data Networking (NDN) is an Information-Centric Networking architecture that has recently attracted significant attention. NDN rethinks the Internet communication paradigm around the name of the data instead of its location. In Content-Oriented architectures, in-network caching enables data retrieval from different network nodes and may result in frequent data sources changes and wide RTT fluctuations...
Most important design parameter in integrated circuit is Power dissipation after speed. Adders are one of the basic fundamental component in such circuit, designing much efficient Adder results in optimizing whole circuit. Due to rapid growth in technology there is a need of fast processing arithmetic unit, so Carry Select Adder (CSLA) is one of the fast processing adder. By observing the CSLA circuitry...
A multiplier requires an Adder circuitry to add carry of previous result to next stage to form partial products and to get final result of multiplication. This paper presents a novel way to implement Line Multiplier without using Adders. The Adder-less Multiplier is implemented on both CMOS and FPGA platforms. In ASIC paradigm CMOS 90nm technology and on FPGA platforms Spartan-3 have been used for...
Power is one of the most important design parameter after speed, in integrated circuit. One of the basic fundamental component in such circuit is adder and subtractor. In order to optimize such circuits there is need of designing efficient and low power fundamental blocks. As per the Launder's principle, KTln2 heat is dissipated if there is any loss in bit. Excess-3 code is one of the sequential codes...
Built in Logic Block Observer (BILBO) is a bank of flip-flops which are used for self-testing for complex digital IC's in pipeline approach. As per the Launder's principle, KTln2 heat is dissipated if there is any loss in bit. Since BILBO is designed with irreversible logic gates we observe large amount of leakage power which affects its performance. So by keeping this as main criteria, our paper...
SRAM have become vital part of many VLSI chips. This in particular is true for many microprocessors, where the on chip memory size is growing with every generation to reduce the constant variance in speeds of processor and main memory. Due to improved integration, operating speeds and power dissipation have become important factors to consider in designing. In process of reducing power and delay change...
This paper proposes a fully Digital, Analog-to-Digital Converter (FD-ADC) which is designed by using UMC's 180 nm digital CMOS technology. The advantages of the digital ADC are its simplicity and low complexity. Power dissipation is also very less compared to other ADC architectures. The FD-ADC is suitable for low power applications and where the input signal swing is small. FD-ADC also needs very...
With the emerging demands for the large-scale services, Device-to-Device (D2D) communication has been viewed as a promising technology to improve the network capacity and user experience. In particular, the peer discovery is the first step to establish a D2D communication. Considering that quality of experience (QoE) is an important metric in video services, We propose a QoE-driven peer discovery...
This paper presents an analytical model for analyzing the performance of the TDMA-based distributed reservation protocol for wireless multi-hop ad hoc networks. A novel three-way handshake process is presented which considers the hold-off and competition process before the transmission of scheduling messages. An explicit expression of expectation of the average delay of the three-way handshake process...
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