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Implementation design space of piece-wise linear outphasing signal component separator is explored by utilizing the changes in micro-architecture, choice of storage elements and aggressive back-end leakage power optimization techniques. With combination of these techniques, ∼2× energy and area savings are achieved, resulting in record energy-efficiency of 32pJ/sample for asymmetric multilevel outphasing...
This paper presents the implementation and measurement results of a power amplifier with passive load modulation targeting Femtocell base station applications and integrated in SOI CMOS 130nm process. The proposed structure combines a SOI LDMOS power stage with a SOI CMOS Tunable Matching Network (TMN) based on high voltage switched capacitors in order to improve PA efficiency at back-off power. At...
A mm-wave IQ power-DAC is reported at W-band. The circuit, which is fabricated in a 45-nm SOI CMOS technology, employs a novel series-stacked Gilbert-cell output stage with gate finger segmentation to directly modulate an 80–95 GHz carrier in amplitude and phase with 8 bits of resolution. Each bit can be switched up to at least 15 Gb/s for an aggregate data rate of 120 Gb/s. A 9-th bit turns the DAC...
A high-voltage (3 V) driving 60 GHz power amplifier (PA) for direct-conversion transceiver using standard 90 nm CMOS technology is reported. The PA comprises two cascode stages with inductive load and low-impedance inter-stage matching, followed by a common-source output stage. To increase the saturated output power (Psat) and power-added efficiency (PAE), the output stage adopts a two-way power dividing...
This paper presents the design of a monolithic 1.9 GHz, Class E, power amplifier (PA) for wireless application with the main components on chip. A cascode topology is used to attenuate transistor stress and to increase the output power, although it compromises the efficiency due to the dissipative process caused by transistor parasitic capacitances. The proposed PA was developed in a single-ended...
A high voltage MESFET transistor has been fabricated using a commercial 45nm SOI foundry. The device has a breakdown voltage >25X the nominal CMOS and is shown to be radiation tolerant to 1Mrad.
Digital polar transmitter concepts based on RF-DA-converter recently proved the potential to significantly reduce power consumption. Furthermore, external component count as well as PCB area is minimized since no TX SAW filter is required and a single multimode, multiband power amplifier can be used.
A 79 GHz power amplifier (PA) using 4-stages common-source structure is presented in this paper. To evaluate temperature dependence of circuit characteristics, the PA is measured at various temperatures. At room temperature (RT) and 100°C, the saturated output power is 7.6 and 7.1dBm, the maximum PAE is 6.2% and 4.9%, respectively. The reliability and lifetime of PA is also obtained. To the author's...
Cascode class-E power amplifier in 180/350 nm CMOS for envelope elimination and restoration system is presented. Designed amplifier achieves 21 dBm output power and 44% PAE at 1900 MHz with 3 V supply voltage. Charging acceleration technique is used for efficiency enhancement. ESD protection problem is discussed.
A fully integrated 60GHz CMOS PA with a PSAT of 22.6dBm is presented. To our knowledge, this is the highest reported PSAT at mm-waves in standard CMOS. To achieve a high power level, 32 differential PAs are combined through a network of transmission lines, Wilkinson combiners, and a multi-port argyle transformer. This method of combining minimizes loss while implementing a low impedance load (~12Ω)...
Towards wide bandwidth and high output power density for 60GHz PA design in 65nm CMOS, this paper introduces a 2D differential power combining network by metamaterial-based zero-phase-shifter. Simultaneous distributed amplification and power combining can be achieved with improved performances in both power density and bandwidth. The PA measurement results show 13.2 dB gain, 8.7% PAE, 13dBm P1dB,...
A 45GHz 64QAM system-on-chip (SoC) CMOS transmitter with digitally-assisted power amplifiers (DAPA) is presented. The SoC includes a 7M gate ASIC with 9b reconfigurable symbol mapping, 8X upsampling, 161tap pulse shape filtering, IQ imbalance correction and DAPA envelope/time estimation. The ASIC feeds two 10b IQ current-steering DACs and active IQ modulator. A unique transformer splitting up converter...
A fully integrated Doherty power amplifier at 2.535 GHz is presented in 65 nm CMOS technology with constant PAE over a 8.75dB backoff. Electromagnetic models of each layout path were included in the optimization to dimension circuit components regarding parasitics of an accurate model. The method increased the PAE level in 6% through a constant 8.75 dB backoff range and increased in 2 dB the output...
A compact energy transmission system in 40nm standard CMOS is presented. The system consists of a 60GHz VCO followed by a quad-core power amplifier as transmitter and an RF-to-DC converter as receiver. The total power delivered by the quad-core PA to its four 500 loads is 24.6dBm. The receiver is a complementary cross-coupled rectifier with a measured efficiency of 28% while supplying lmA of current...
A CMOS linear PA for IEEE 802.11 b/g applications is implemented in a 0.13 μm process including all matching networks. An adaptive power cell (APC) scheme is proposed to achieve high linear output power and efficiency and applied to the PA, which delivers the output power of 20.5 (19.5) dBm with the PAE of 20.2(17.5)% for an 802.11g modulated signal with the EVMs at −25(−28) dB.
A novel stacked FET digital-to-RF converter is implemented in 45-nm SOI CMOS, which shares DC current through an I/Q digital-to-analog converter (DAC), I/Q mixer, and stacked-FET PA to provide high output power. The proposed architecture transmits at 1.25 Gbps for QPSK at 45GHz. This transmitter exhibits a 21.3-dBm saturated output power, while achieving a peak PAE of 16%. The circuit occupies 0.3mm...
A tunable and highly digital RF frontend for multi-band TDD radios is integrated in 45nm SOI CMOS. The PA absorbs the TX branch of the TX/RX switch with no added loss. Peak PA output power is 27.5±0.5dBm from 1.6 to 3.4GHz, with up to 30% total efficiency at 2V. For TDD LTE applications, better than −30dBc ACLR and −25dB EVM is measured with 16-QAM, 20MHz signals from 1.65 to 3.5GHz, with up to 16...
Although a CMOS device has inferior characteristics for PA it allows versatile controls and possible integrations with other circuits. These advantages surely provide us various methods to linearize a PA with resultant high efficiency. Several linearization methods of RF CMOS PAs are introduced in this paper. These are mostly based on adaptively controlling the biases of common source and common gate...
A 1.75GHz CMOS Doherty power amplifier (PA) is presented. This Doherty PA uses voltage combining method that is different from the conventional current combining Doherty amplifier based on HBT. The output transformer is employed to combine the output power and realize the load modulation. The proposed CMOS Doherty PA is fabricated in 180nm CMOS process. Simulation results show that the output transformer...
This paper presents a highly efficient power amplifier (PA) using the envelope tracking (ET) technique for 3G W-CDMA applications. The PA is designed in the IBM 0.35-µm SiGe BiCMOS process with through-silicon-via (TSV). The CMOS envelope modulator IC is designed and fabricated in the TSMC 0.35-µm SiGe BiCMOS process. The ET-PA system achieves an overall composite power-added-efficiency (PAE) of 35...
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