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Low-temperature aluminum-germanium (Al-Ge) eutectic bonding has been investigated for monolithic three-dimensional integrated circuits (3DIC) applications. Successful bonds using Al-Ge bilayer films as thin as 157 nm were achieved at temperatures as low as 435degC, when applying 200 kPa down-pressure for 30 minutes. The liquid phase of the eutectic composition ensured a seamless and void-free bond...
A ruthenium (Ru) film was deposited by physical sputtering in an N2 atmosphere on a low-k SiOC dielectric film. This Ru deposition process modified the surface of the underlying low-k SiOC to a higher density SiOC(N) layer of approximately 3 nm thickness. This combined SiOC(N) / Ru stack showed good barrier properties without the need of any other barrier layer. This new stack structure removes the...
In search of solar cell concepts that allow processing thinner wafers (<150 micron), the conventional full Al rear side is replaced by an open rear metallization combined with a dielectric passivation layer. We show a gain of 2.1% (relative) in the product of Jsc??Voc, when we apply a passivated SiNx dielectric layer and local Al contacts on the rear of p-type mc-Si solar cells instead of a full...
Semiconductor (e.g. silicon, germanium) nanowires have gained interest as an attractive platform to fabricate field effect transistors devices because of their reduced short channel effects by comparison to planar devices. The realization of high performance nanowire devices however has been stymied primarily by large source (5) and drain (D) contact resistances. Here we report the fabrication and...
In this paper we describe the procedure to sputter low acoustic impedance SiO2 films to be used as low acoustic impedance layer in Bragg mirrors for BAW resonators. The composition and structure of the material are assessed through infrared absorption spectroscopy. The acoustic properties of the films (mass density and sound velocity) are assessed through X-ray reflectometry and picosecond acoustic...
In this work, diamond films were grown on TiSi2 surface coated on Si substrate using hot-filament CVD method. It is demonstrated that at the same condition, (001) textured diamond nuclei can be formed on Si and TiSi2 surface, however, when diamond films was grown on Si substrate, the (100) facet has a high growth rate, while as for the case of TiSi2 substrate, the (111) facet of diamond grows faster...
At a given thickness of HfO2, atomic layer deposited (ALD) TaN metal-gates showed higher equivalent oxide thickness (EOT) and flat-band-voltage (Vfb) shift compared to physical vapor deposited (PVD) TaSiN after annealing at 750degC for 30 min in N2. TEM data revealed the growth of a thicker interfacial oxide of 1.7 nm for TaN compared to 0.9 nm for TaSiN. In addition, TaN showed higher effective workfunction...
We demonstrate for the first time Schottky barrier height (SBH) tuning using interfacial SiO2/high-kappa dipoles resulting in SBH les 0.1 eV from the conduction band-edge (CBE) and SBH les 0.2 eV from the valence band-edge (VBE). The near band-edge electron and hole SBHs have been obtained using a dielectric-dipole mitigated (DDM) scheme with single metal on Si junction. By optimizing the dielectric...
Optical sum-frequency generation and ferroelectric-like switching in Si-O polar structures comprised of Si nanocrystals (nc-Si) in mesoporous silica was reported and attributed to polar layers lying at the interfaces between one-side bounded nc-Si and host.
Direct patterning of silicon dioxide by electron beam lithography is used for the definition of metal nanojunction on wires fabricated on silicon on insulator (SOI) substrates. Devices based on a single silicon nanowire as small as 15 nm and several micrometers long are fabricated by means of a top down process based on electron beam lithography, silicon anisotropic etching and thermal oxidation....
Group IV elements and their alloys show poor light emission due to their indirect gap. Application of tensile strain in Ge lowers the ?? valley below the L valleys in bulk as well as in Ge nanowires. We present also our results on direct gap type I alignment showing direct gap at ~ 0.8 eV in Si1-p-qGep Cq (C <4%) active layers with Ge1-x-ySixSny as the barrier. We have chosen a composition to give...
The emission peaks and their intensity distributions of plasmonic thermal emitters with top metal perforated by hole array arranged in rhombus lattice had been investigated theoretically and experimentally. The intensity distribution of emission peaks follows blackboday radiation but becomes weaker if the coupling of the neighboring two peaks occurs.
Porous silicon (PS) of various morphologies is used as template for electrochemical deposition of distinct metals, especially ferromagnetic ones. The precipitation of Ni and Co under various process parameters leads to nanocomposites consisting of ferromagnetic metal-structures embedded in the PS-templates. These specimens are tunable in their morphology by the electrochemical fabrication parameters...
Application of tensile strain in Ge lowers the G valley below the L valleys but the direct gap is reduced from the value in unstrained Ge. We considered Ge1-qCq (C <4%) active layers with Ge1-x-ySixSny as the barrier and estimated the range of compositions in the active and barrier layers to yield direct gap (~0.8 eV) type I alignment by using model solid theory. We have chosen a composition to...
MOS capacitor structure with double-layer heterogeneous nanocrystals consisting of metal and semiconductor embedded in gate oxide for the applications of nonvolatile memory have been fabricated and characterized. By combining the self-assembled Ni nanocrystals and vacuum electron-beam co-evaporated Si nanocrystals in SiO2 matrix, the MOS capacitor with double-layer heterogeneous nanocrystals can appear...
In blast furnace (BF) ironmaking process, silicon content in hot metal is an important index, which reflects the thermal state of BF. To predict the silicon content in hot metal effectively and level up the forecasting accuracy, a novel combined model based on empirical mode decomposition (EMD) and support vector machine (SVM) is proposed. Firstly, the time series data of silicon content in hot metal...
The temperature dependence of device performance is a critical factor that determines overall product power-performance. We show HKMG gate stacks drive significantly higher threshold temperature dependence over poly-Si/SiON. We further show that in SOI, the work-function engineering enabled by HKMG integration schemes can result in even higher Vt temperature sensitivity attributed to differences in...
A process development for stretchable silicon electronics encapsulated in a layer of polydimethylsiloxane is presented. Stretchability is achieved by segmenting the normally rigid silicon substrate into small islands (<2??2 mm2) and connecting these by flexible metal interconnects. The metal interconnects have a mesh shape providing stretchability and improved reliability. The mesh-shaped interconnects...
We present a systematic examination of Vth controllability using Y2O3, La2O3, and MgO2 layers by atomic-layer-deposition (ALD) technology with HfSiON/TaSiN gate first stacks for half-pitch (hp) 32 nm-node metal gated bulk devices. By employing base-Y2O3 layers of 1 mono-layer (ML< 0.5 nm), ultra-thin equivalent-oxide-thickness (EOT: 0.72 nm) can be achieved with excellent Vth controllability (|DeltaV...
A new model to understand the origin of the dipole formed at high-k/SiO2 interface is presented. In our model, the areal density difference of oxygen atoms at high-k/SiO2 interface is considered as the cause of the dipole. On the basis of our model it is possible to predict the dipole direction and its magnitude for the candidate gate dielectrics, including ones so far not experimentally reported...
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