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Silicon Carbide (SiC) is a compound semiconductor has ten times the dielectric breakdown field strength, three times the band-gap, and three times the thermal conductivity of silicon (Si). SiC MOSFETs can be operated at higher switching frequencies and higher ambient temperatures than Si MOSFETs. This paper deals with design, fabrication and testing of a gate driver circuit for driving SiC power MOSFETs...
This paper presents a zero voltage switching (ZVS) passive snubber circuit for the MOSFET used in conventional boost converter which consists of an inductor, a capacitor, a resistance and a diode. It helps in improving the high current and voltage stress. With the help of this circuit, power conversion efficiency is improved by controlling the voltage and current in the switch, thus providing zero-voltage...
Compared with the silicon semiconductors, silicon carbide (SiC) metal-oxide-semiconductor Field-Efïect transistor (MOSFET) can operate at higher switching frequency and higher temperature, which makes the junction temperature estimation more significant and challenging. In this paper, different thermo- sensitive electrical parameters (TSEPs) are investigated about their potential to measure the junction...
High temperature (HT) gate driver is a key technology for the motor drive application for electrical vehicle (EV) in HT environment. Based on the available HT devices, this paper introduces the design of HT gate driver for SiC MOSFET. The gate driver architecture with isolation function is discussed first. Then, gate driver hardware design is presented. Besides the basic driving function of driving...
The clock distribution network consists of the clocked tree and flip flops. In this paper we have designed sense amplifier energy recovery (SAER), static differential energy recovery (SDER), differential conditional capturing energy recovery (DCCER), signal conditional capturing energy recovery (SCCER) and self gated energy recovery (SGR) flip flops. Among these flip flops SGR flip flop is giving...
In this paper, we provide an efficient method to improve the subthreshold characteristic of silicon-on-insulator (SOI) MOSFET using a vertical non-uniform doping profile for the drain region. Two different structures are simulated: uniform-drain (UD) and gaussian-drain (GD) SOI MOSFET and results are compared. Gaussian distribution function parameters such as peak doping density (Np) and standard...
In this paper, twin gate rectangular recessed channel (TG-RRC) MOSFET with independent gate control is used to realize its application in digital electronics by using it as two input logic. The input logic is controlled by the independent gates which have different work functions (Φ1 for gate 1 and Φ2 gate 2) which are separated by oxide layer of 2 nm, thus controlling various electrical parameters...
This work discusses the effectiveness of high-k dielectric as gate stack in transparent gate recessed channel (TGRC) MOSFET having 20nm gate length. The main aim of this study is to analyse the reliability issues of TGRC MOSFET in terms of analog parameters. Results indicate that with the incorporation of HfO2 as gate stack on SiO2, on-current enhances significantly whereas leakage current (off-current)...
In this paper, we have demonstrated the electrical characteristics of Si Gate-All-Around (GAA) Nanowire (NW) field-effect transistor (FET) using numerical simulation. GAA devices are considered to be the ultimate architecture among all multi-gate devices. During fabrication, the cross-section of a GAA device may be elliptical instead of perfectly circular. The effective diameter of such elliptical...
This paper examines the reliability issues of In2O5Sn (ITO) gate electrode (Transparent Gate) Recessed Channel (TGRC) MOSFET by considering the influence of interface trap charges polarity and density present at the Si/SiO2 interface. The reliability of TGRC MOSFET is observed in terms of Linearity and distortion FOMs such as gm, gm3, VIP3. IIP3, HD3. IMD3. Results so obtained revealed that the existence...
As the process of device is scaling down continually. Engineers are trying their best to challenge the limitations of physics in IC industry. However, power IC like power MOSFET and Insulated Gate Bipolar Transistor (IGBT) still have a high requirement despite device scale — downs. Here, we want to highlight a method to improve defect location in IGSS (Gate — Source leakage) failure, through this...
A simulation study is conducted to model the behavior of the MOS transistor output response with a resistive defect on gate, with both DC and pulse signal inputs. Nanoprobing is performed on actual transistors in DC and pulse modes to validate the simulation. Compared to a reference transistor, a more resistive gate corresponds to a larger rise time in the dynamic pulse response, while the static...
The paper has analyzed the problems discovered in the application validation of a certain NOR FLASH for aerospace use, and clarified that the failure of this FLASH belongs to bit interference caused by over-erase. At the same time, the failure mechanism has also been analyzed, which is found to be discreteness of chip manufacturing process and incomplete coverage of the test; additionally, evasion...
This paper presents a high drivability of full adder with less area and power consumption. This GDI based full adder is implemented by using both gate diffusion input (GDI) technique and pass transistor logic that leads to be a reduced area and power. To reducing the static power, ultralow power diode (ULPD) is used. The leakage current of this diode lies within the range of pA. The comparison has...
In this paper, we present a method for hardening memory and sequential cells against soft errors. The effect of the ionizing particle on the bulk potential is exploited to prevent the induced SET from propagating in the circuit. The proposed method requires a minimum number of extra transistors. The solution is applied to D Flip-Flop design, and alpha and heavy-ions test results are presented.
This paper describes the case study of test method of gate source failure and the fault localization approach with aid of device physics theory. The nominal behaviour of IGBT device is turn on the moment gate voltage reaches the threshold voltage. However, in this case the device turn on before the gate voltage reaches to the ideal threshold voltage due to distracted by Gate-source capacitance. On...
Reliability of Superjunction (SJ) MOSFET is closely related to its manufacturing process. Experiments are carried out to investigate the electrical characteristics in high temperature of SJ MOSFET produced by deep trench filling technology. Filling holes are confirmed to be responsible for the performance deterioration in high temperature and the mechanism has been analyzed thoroughly.
The influence of forward current freewheeling time on the reverse recovery di/dt robustness of Superjunction (SJ) MOSFET body diode is investigated in detail. It is found that the maximum di/dt capability of body diode is improved dramatically with reducing the forward current freewheeling time. To explore this phenomenon, physical TCAD simulations and experiments have been carried out. It shows that...
A novel electrostatic discharge (ESD) clamp circuit for power-rail ESD protection, consisting of the stacked transistors and biased RC network, is proposed in a 90 nm CMOS process. The biased RC network possesses a small footprint and the detection circuit has a pretty low leakage current of up to 12 nA under normal operation. The proposed ESD clamp circuit has a long hold-on time of 800 ns under...
Butting and inserted pickup layout in MOSFETs leads to substrate resistance shunting effect and serious ESD robustness degradation. This work develops novel layout with external well/ diffusion resistance embedding between the substrate and the grounding terminal in the NMOS transistors. This layout method can greatly enhance ESD performance of the inserted pickup devices. The second breakdown current...
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