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Multiprocessor platforms are gaining markets as a solution to boost general performance of processor beyond technological limitations that are present in single processors chips, Multi-processor in embedded systems also have a future in particular with applications like SDR(Software Defined Radio) where both high performance and high adaptability are required. Cryptographic algorithms implementation...
In the numeric communication, much devoted efforts are dedicated to improve security and safety of numeric transactions. Hardware implementation of cryptography algorithm, as the AES, is a good solution to preserve confidentiality and accessibility to the information. In this context, this paper proposes an optimal hardware implementation of AES algorithm. Taking advantages of dynamic partially reconfigurable...
In this paper we investigate the performance of the block cipher PRESENT on FPGAs. We provide implementation results of an efficiency (i.e. throughput per slice) optimized design and compare them with other block ciphers. Though PRESENT was originally designed with a minimal hardware footprint in mind, our results also highlight that PRESENT is well suited for high-speed and high-throughput applications...
This paper describes the role of security policies for FPGAs. The FPGA development specifics and a short overview of threats against systems security are presented. We propose a security policy consisting of three parts, first: addressing the general security demands, second: the communication between FPGA and the peripheral devices, and third: the behaviour inside the FPGA. The different methods...
Modular Exponentiation is at the heart of various arithmetic architectures used in most Public Key cryptography algorithms. Modular Exponentiation of large numbers requires excessive processing. An efficient implementation of modular exponentiation may help overcome the speed issues of public Key Cryptography. in this work, the most promising technique of Montgomery modular exponentiation and its...
In the next years, new hash function candidates will replace the old MD5 and SHA-1 standards and the current SHA-2 family. The hash algorithms RadioGatun and irRUPT are potential successors based on a stream structure, which allows the achievement of high throughputs (particularly with long input messages) with minimal area occupation. In this paper, several hardware architectures of the two above...
In this paper, techniques to perform power analysis attacks to snatch confidential data from cryptographic circuits are quantitatively compared. In particular, the popular Differential Power Analysis (DPA) and Correlation Power Analysis (CPA) techniques are compared in terms of their effectiveness, explicitly considering both precharged and static logic styles. The analytical evaluation of the main...
This paper presents FPGA implementation and overhead evaluation for an algorithmic DPA countermeasure for advanced encryption standard AES. To reduce implementation overhead the masked compact S-Box, proposed by Canright, was chosen to implement a DPA countermeasure on an SRAM FPGA. Obtained results showed that secured AES IP leads to slices number increase by 60,1% and a frequency decrease by 4%.
Security devices can reveal critical information about the cryptographic key from the power consumption of their circuits. Differential power analysis (DPA) is one of the most effective power analysis techniques. In recent years numerous countermeasures against the DPA attack of hardware implementations of security algorithms have been proposed. In this paper, we investigate the random delay insertion...
The hardware - software codesign of cryptosistems, is the best solution to reach a reasonable yield in systems with resources limitation. In the last years, the cryptosistems based on elliptic curves (CEE) have acquired an increasing importance, managing at present to form a part of the industrial standards. In the underlying finite field of an CEE squaring and field multiplication is the next computational...
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