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We propose an approximate logic synthesis heuristic for synthesizing a 2-SPP circuit under a given error rate threshold. 2-SPP circuits are three-level EXOR-AND-OR forms with EXOR gates restricted to fan-in 2. They represent a direct generalization of SOP forms, obtained generalizing cubes to "2-pseudocubes" where literals in cubes may be replaced by 2-EXOR factors in 2-pseudocubes. We discuss...
With shrinking process technologies, the likelihood of mid-life faults in combinatorial logic is increasing. Approximate logic functions are a promising approach to mitigate such faults as the technique can be applied to any digital circuit, it protects against multiple fault models and offers a trade-off between increased area and fault coverage. In this paper we present a new algorithm for generating...
Evaluating the coverage of tests for large circuits is computationally very intensive, particularly for logic BIST, software-based self test and on-line test schemes. This has led to research into techniques for rapidly evaluating the coverage of proposed test. We introduce a new metric which is highly correlated with fault coverage measured by gate-level simulators. Based on this metric, we estimate...
A key problem in post-silicon validation is to identify a small set of traceable signals that are effective for debug during silicon execution. Most signal selection techniques rely on a metric based on circuit structure. Simulation-based signal selection is promising but have major drawbacks in computation overhead and restoration quality. In this paper, we propose an efficient simulation-based signal...
Addition is a fundamental function in arithmetic operation; several adder designs have been proposed for implementations in inexact computing. These adders show different operational profiles; some of them are approximate in nature while others rely on probabilistic features of nanoscale circuits. However, there has been a lack of appropriate metrics to evaluate the efficacy of various inexact designs...
The problem of hardware Trojan detection has been recently studied extensively. The use of traditional testing strategies to detect hardware Trojans is not effective because the probability of triggering a hardware Trojan during testing is very low. Moreover, the small size of the Trojan compared to the overall size of the chip reduces the impact of the Trojan on side channels such as static and dynamic...
In both pre-silicon and post-silicon validation, the detection of design errors requires both stimulus capable of activating the errors and checkers capable of detecting the behavior as erroneous. Most functional and code coverage metrics evaluate only the activation component of the testbench and ignore propagation and detection. In this paper, we summarize our recent work in developing improved...
In simulation-based validation, the detection of design errors requires both stimulus capable of activating the errors and checkers capable of detecting the behavior as erroneous. Validation coverage metrics tend to address only the sufficiency of a testbench's stimulus component, whereas fault insertion techniques focus on the testbench's checker component. In this paper we introduce “coverage discounting”,...
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