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In a computer system, the fastest storage component is the CPU cache, followed by the system memory. I/O to disk is thousands of times slower than an access to memory. This fact is the key for why you try to make effective use of memory whenever possible and defer I/Os whenever you can. The majority of the user response time is actually spent waiting for a disk I/O to occur. By making good use of...
Stochastic computing (SC) [1] has received attention recently as a paradigm to improve energy efficiency and fault tolerance. SC uses hardware-generated random bitstreams to represent numbers in the [0:1] range - the number represented is the probability of a bit in the stream being logic-1. The generation of random bitstreams is typically done using linear-feedback shift register (LFSR)-based random...
A large number of hardware faults are being caused by an increasing number of manufacturing defects and physical interactions during operation. This poses major challenges for the design and testing of modem Multiprocessor System-on-Chips (MPSoCs). Intermittent faults constitute a major part of hardware faults and their fault rates can be used as an indicator of the wear-out in a Processing Element...
The advent of software-based fault tolerance presents a rare opportunity to create a new paradigm for support equipment architecture. This test system must be capable of servicing the development, integration, and test of hardware and software, allowing developers remote access to the units under test (UUT) throughout the integration and test process. Using mainly low-cost commercial off the shelf...
Since the before birth of computers we have strived to make intelligent machines that share some of the properties of our own brains. We have tried to make devices that quickly solve problems that we find time consuming, that adapt to our needs, and that learn and derive new information. In more recent years we have tried to add new capabilities to our devices: self-adaptation, fault tolerance, self-repair,...
To achieve better performance, computer designers employ advanced techniques that shrink feature sizes, lower supply voltage, increase clock rates and memory capacity, and meanwhile modern computers become increasingly vulnerable to soft errors caused by energetic particles, such as alpha particles and neutron strikes. Therefore, fault tolerance evolves into one of the most significant design objectives,...
In safety-critical environments it is no longer sufficient to rely on legacy methodologies. Correctness should be built in all the way through the process. This paper presents a toolchain which allows theorem prover output to be interfaced to fault-tolerant FPGA circuitry. We show a shallow embedding of a lambda calculus executing on a Xilinx platform with the assistance of a choice of fault-tolerance...
Fault injection has been an important mechanism to test the dependability properties of a system. Through this mechanism, it is possible to analyze the behavior of a computer program in case of anomalies and to obtain useful statistics to measure the effectiveness of techniques for fault tolerance. In areas such as telecommunications, aviation and finance, the use of fault tolerance is a common practice,...
With the popularization of multi-core processors, transaction memory, as a concurrent control mechanism with easy programing and high scalability, has attracted more and more attention. As a result, the reliability problems of transactional memory become a concerning issue. This paper addresses a transactional implementation of the Lu benchmark of SPLASH-2, and proposes a fault-tolerant Lu algorithm...
This paper is concerned with increasing the reliability with respect to debris impact of computing systems on board satellites using Fault Tolerant Distributed Computing. A novel adaptive middleware for fault-tolerance (AMFT) design is presented. The middleware performs failure detection, isolation and recovery and synchronizes the operation of a distributed On-Board Computer (OBC) system. If one...
Soft errors on hardware could affect the reliability of computer system. To estimate system reliability, it is important to know the effects of soft errors to system reliability. This paper explores the effects of soft errors to computer system reliability. We propose a new approach to measure system reliability for soft error factor. In our approach, hardware components reliability is concerned first...
A new signal control system for railway stations, fault-tolerant all- electronic computer interlocking control system, is proposed,in which the computer-based interlocking system layer is constituted through the implementation of electronic security unit replacing the Relay, and the all-electronic fault-tolerant controlling for whole system is fulfilled through two of three fault-tolerant computer...
Data intensive computing is having an increasing awareness among computer science researchers. As the data size increases even faster than Moore's Law, many traditional systems are failing to cope with the extreme large volumetric datasets. In this paper we use a real world graph processing application to demonstrate the challenges from the emerging data intensive computing and present a solution...
Commercial off the shelf processors are becoming mandatory in space applications to satisfy the ever-growing demand for on-board computing power. As a result, architecture able to withstand the harshness of the space environment are needed to cope with the errors that may affect such processors, which are not specifically designed for being used in space. Beside design and implementation costs, validation...
This paper presents a case study that aims to develop a hardware architecture for the computer to the ITASAT university satellite, based on fault-tolerant architecture and calculations of reliability. The on-board computer of a satellite, inserted into the on Board Management Subsystem, has functions of receiving, processing and distribution of commands to the subsystems and payload of the satellite;...
In this paper we are presenting a journaling mechanism to improve dependability of a stack processor. This approach is based on a HW/SW mixed mechanism, using hardware error detection and software error correction. The SW correction is based on a rollback mechanism and relies on a journal. The journal is located between processor and the main memory in a way that all the data written into the main...
This article presents a precise synchronization algorithm based on status tracking and locking mechanism. Tracking execution state of triple computer and running state of time base counter through dual state machine not only can implement precise synchronization of TMR computer, making status synchronization precision and time-base synchronization precision below 30ns, but also save valuable interconnection...
Very large scale integration (VLSI) technology has evolved to a level where large systems, previously implemented as printed circuit boards with discrete components, are integrated into a single integrated circuit (IC). But aggressive new chip design technologies frequently adversely affect chip reliability during functional operation. Reliability is of critical importance in situations where a computer...
This talk will summarize our design for reliability initiatives that anticipate the paradigm shift to error-aware and error-tolerant design of integrated circuits, both of which are required to address the problem of increasing hardware failures in future technology nodes. These concerns are only exacerbated as we look forward to emerging technology alternatives. Using graphene as an example, I will...
Scaling in hardware integration process results in IC-process geometry reductions, lower operating voltages and increased clock speeds. This paper first surveys the reliability obstacles these developments give rise to and then points out that computing systems can no longer be safely assumed to fail only by crashing. Yet this assumption is at the core of primary-backup replication which the literature...
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