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The Kiwi project revolves around a compiler that converts C# .NET bytecode into Verilog RTL and/or SystemC. An alpha version of the Kiwi toolchain is now open source and a user community is growing. We will demonstrate an incremental approach to large system assembly of HLS and blackbox components, based on an extended IP-XACT intermediate representation. We show how to address multi-FPGA designs...
Chisel is a hardware construction language that supports a simplistic level of transactional programming via its Decoupled I/O primitives. In this paper we describe extensions that layer popular design paradigms on the Chisel substrate. We include RTL, SAFL-style functional hardware description, Handel-C message passing and Bluespec rules. We then briefly discuss interworking between these design...
In safety-critical environments it is no longer sufficient to rely on legacy methodologies. Correctness should be built in all the way through the process. This paper presents a toolchain which allows theorem prover output to be interfaced to fault-tolerant FPGA circuitry. We show a shallow embedding of a lambda calculus executing on a Xilinx platform with the assistance of a choice of fault-tolerance...
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