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In this paper we present a new technique to dynamically adapt the first step (broad phase) of the collision detection process on hardware architecture during simulation. Our approach enables to face the unpredictable evolution of the simulation scenario (this includes addition of complex objects, deletion, split into several objects, ...). Our technique of dynamic adaptation is performed on sequential...
Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, multicore machines are dominating the architectural spectrum in various application domains. These two trends require a fresh look at resiliency of multithreaded applications against transient errors from a software perspective. In this...
Cloud Computing is one of the hottest topics researched today, with the objective of taking advantage of data center computational resources. Hardware and software virtualization make the environment scalable, redundant, and lower cost. This paper intends to characterize scientific and transactional applications in Cloud infrastructures IaaS, identifying the best virtual machine configuration in terms...
Technology scaling is having an increasingly detrimental effect on microprocessor reliability, with increased variability and higher susceptibility to errors. At the same time, as integration of chip multiprocessors increases, power consumption is becoming a significant bottleneck that could threaten their growth. To deal with these competing trends, energy-efficient solutions are needed to deal with...
One of the major problems associated with integrating multiple cores on a single chip is the performance demand it places on the interconnect system because of the combined traffic generated by multiple simultaneously executing threads. In this paper, we analyze interconnect compression potential in the two primary types of information - instructions and data - and important interconnect components...
Technology trends enable the integration of many processor cores in a System-on-Chip (SoC). In these complex architectures, several architectural parameters can be tuned to find the best trade-off in terms of multiple metrics such as energy and delay. The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation...
The trend towards multi-/many- core design has made network-on-chip (NoC) a crucial component of future microprocessors. With CMOS processing technologies continuously scaling down to the nanometer regime, effects such as process variation (PV) and negative bias temperature instability (NBTI) significantly decrease hardware reliability and lifetime. Therefore, it is imperative for multi-core architects...
Multi-core architecture has become a mainstream in modern processor and computation-intensive chips. A widely-used multi-core architecture contains identical cores. This paper proposes a low-cost and scalable test architecture for a multi-core chip with identical cores. The test architecture provides test scalability by using a two-dimensional pipelined test access mechanism (TAM). Also, some scan...
Modern high performance computing systems are being increasingly deployed in a hierarchical fashion with multi-core computing platforms forming the base of the hierarchy. These systems are usually comprised of multiple racks, with each rack consisting of a finite number of chassis, and each chassis having multiple compute nodes or blades, based on multi-core architectures. The networks are also hierarchical...
In this article we present a study on an implementation, named clAES, of the symmetric key cryptography algorithm Advanced Encryption Standard (AES) using the Open Computing Language (OpenCL) emerging standard. We will show a comparison of the results obtained benchmarking clAES on various multi/many core architectures. We will also introduce the basic concepts of AES and OpenCL in order to describe...
NLP search takes a long amount of time due to large size of corpus, besides there are too many hits at the server. At present, the strategy to deal with search engines is to have many thousands of servers in order to provide real-time searches. Fast alternatives are therefore sought. In this paper, we present a pioneering work in this direction by taking word stemming, a crucial aspect of search and...
Vehicle-based pedestrian detection system receives more and more attentions in road safety applications of the modern intelligent transportation system. However, the existed detection algorithms are too computing extensive for single core vehicle-based processors. As the promising multi-core architecture provides both energy efficient and powerful computing solutions, it is relevant to evaluate the...
We present a design for a hardware supported global synchronization unit that would be implemented on-chip and directly accessible by all processors in a multi-core architecture. This global synchronization unit will provide all processors with access to global state information from all other processors in just a few clock ticks, and can be used to perform highly efficient and scalable time synchronization...
Modeling and simulation has been used in science and engineering with theoretical analysis and practical experiments. Generally, these models are represented as partial differential equations(PDEs) which can be solved numerically using meshes and sparse matrices. The solution cost of sparse linear systems, typically, dominates the solution cost of these PDEs. Consequently, an efficient sparse linear...
The parallelization strategy of the Physically-Constrained Iterative Deconvolution (PCID) algorithm is being altered and optimized to enhance performance on emerging multi-core architectures. This paper reports results from porting PCID to multi-core architectures including the JAWS supercomputer at the Maui HPC Center (60 TFLOPS of dual-dual Xeonreg nodes) and the Cell Cluster at AFRL in Rome, NY...
There are two problems emerged while multi-core platform become popular in daily life, no matter for high end or low end. The first is how to fully utilize computing resource of these cores without requirement of large modifications of current software design model. The second is about dividing a piece of serial program into parallel program. However, the latter is the responsibility of compiler,...
With the progress of semiconductor technologies and the advent of multi-core processor, parallel programming models are evolving and the education is needed to help sequential programmers adapt to the requirements of those new technologies and architectures. Now multi-core related contents have been adopted into curricula syllabus of more than 100 universities in China, but how those contents be organized...
Significant improvement to visual quality for real-time 3D graphics requires modeling of complex illumination effects like soft-shadows, reflections, and diffuse lighting interactions. The conventional Z-buffer algorithm driven GPU model does not provide sufficient support for this improvement. This paper targets the entire graphics system stack and demonstrates algorithms, a software architecture,...
With the progress of semiconductor technologies and then the advent of multi-core processors, the age of Serial Computing is over and parallel computing technology is now emerging as mainstream. Parallel programming models are needed to change and the education is need to help sequential programmers adapt to the requirements of this new technology and architecture. Now multi-core related contents...
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