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Approximate memory is a promising technology for emerging recognition, mining and vision applications. These applications require the processing of large volumes of data to achieve energy-efficiency with negligible accuracy loss. This paper proposes a multi-level approximate memory architecture based on data significance analysis. In this architecture, a memory array is divided into several separated...
The resistive random access memory (RRAM) technology is a promising candidate for the replacement of NAND FLASH at ultra-scaled nodes. In this work, the scalability of a 2-layer RRAM cross-point array architecture is explored towards the 10 nm node. Device-circuit co-design methodologies are employed to optimize the array architecture. The impact of sneak paths, IR drop along the wire interconnect...
This paper describes a write-once-memory-code phase change memory (WOM-code PCM) architecture for next-generation non-volatile memory applications. Specifically, we address the long latency of the write operation in PCM — attributed to PCM SET — by proposing a novel PCM memory architecture that integrates WOM-codes at the memory organization and memory controller levels. The proposed <22>2/3...
For the past thirty years, the downscaling has been the guiding principle in the field of High-density semiconductor memories. However, recently, the limit of planar bulk MOSFETs is becoming apparent. Therefore, in order to extend the scalability of memory technology to the nano-scale generation, a new device structure is necessary. From the viewpoint, I will discuss future High density Memory with...
Cross-point memory architecture offers high device density, yet it suffers from substantial sneak path leakages, which result in large power dissipation and a small sensing margin. The parasitic resistance associated with the interconnects further degrades the output signal and imposes an additional limitation on the maximum allowable array size. In this paper, we study the device requirements of...
There has been much work on the next generation of memory technologies such as MRAM, RRAM and PRAM. Most of these are non-volatile in nature, and compared to SRAM, they are often denser, just as fast, and have much lower energy consumption. Using 3-D stacking technology, it has been proposed that they can be used instead of SRAM in large level 2 caches prevalent in today's microprocessors. However,...
Process variation poses a threat to the performance and reliability of the 6T SRAM cell. Research has turned to new memory cell designs, such as the 3T1D DRAM cell, as potential replacement designs. If designers are to consider 3T1D memory architectures, performance models are needed to better understand memory cell behavior. We propose a decoupled approach for collecting Monte Carlo HSPICE data,...
Dynamic cache resizing coupled with built in self test (BIST) is proposed to enhance yield of SRAM-based cache memory. BIST is used as part of the power-up sequence to identify the faulty memory addresses. Logic is added to prevent access to the identified locations, effectively reducing the cache size. Cache resizing approach can solve for as many faulty locations as the end user would like, while...
Aggressive technology scaling to 45 nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly sensitive to process variation due to their high density and organization. Designers typically over-provision caches with additional resources to overcome the hard-faults. However, static allocation and binding of redundant...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
The reliability of advanced embedded non-volatile memories has been discussed using the 2T-FNFN devices example. The write/erase endurance and the data retention are the most important reliability parameters. The intrinsic reliability mechanisms can be addressed through single cell evaluation, while the cell-to-cell variation determines the product level reliability. The cell-to-cell variation can...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
One of the most effective techniques to reduce a processor's power consumption is to reduce supply voltage. However, reducing voltage in the context of manufacturing-induced parameter variations can cause many types of memory circuits to fail. As a result, voltage scaling is limited by a minimum voltage, often called Vccmin, beyond which circuits may not operate reliably. Large memory structures (e...
A novel SRAM architecture with a high density cell in low supply voltage operation is proposed. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 um2 cell in 65 nm CMOS technology demonstrated 0...
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