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2-transistor (2T) cell technology used for embedded non-volatile memory (eNVM) has been scaled down to 40nm node. To enable aggressive cell scaling, the array architecture is modified compared to previous generations and the channel length of cell is drastically reduced requiring steep cell junctions, which give rise to new disturb phenomena. This paper describes how to safeguard the drain disturb...
Performance and large memory space are the most prominent issues highlighted for local DNA sequences alignment. Therefore, this study is an attempt to test the systolic array approach for Smith-Waterman (SW) algorithm for improving the performance of DNA sequence alignment accelerator. The design was developed using LabVIEW and targeted to Xilinx Spartan 3E while the original SW has been used as a...
In this paper, a source to source (S2S) compiler with profiling support is designed and implemented. The focus of this compiler is to convert the source code running in the homogeneous environment to the code that can be compiled and run under the Cell BE architecture. Combined with the runtime profiling mechanism, the S2S compiler records the optimization strategies and their effects, which can be...
In this paper, we introduce a constraint programming-based approach for optimization of routing and reconfiguration overhead for a class of reconfigurable processor array architectures called weakly programmable. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for optimal routing of data between processors...
In this paper, we introduce a constraint programming-based approach for the optimization of area and of reconfiguration time for communication networks for a class of regular 2D reconfigurable processor array architectures. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for the optimal routing of data...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
In terms with the characteristic of real-time control of system on analog signal, propose a statistical control method based on control micro-unit, define a statistical steady coefficient to expend control micro-unit; obtain quantization control state statistical figures by quantization statistical identification; define the average statistical state deviation, statistical trend, statistical overshooting,...
A new CAD environment for the design optimization of static RAMs has been developped. The optimal memory architecture is determined in varying the segmentation of the cell array. Optimal decoding and sensing circuits are chosen from a library. Transistor dimensions are optimized with respect to delay, area and power using analytical optimization techniques. The methods can be applied to all kinds...
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