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Graph analysis applications have been widely used in real services such as road-traffic analysis and social network services. Breadth-first search (BFS) is one of the most representative algorithms for such applications; therefore, many researchers have tuned it to maximize performance. On the other hand, owing to the strict power constraints of modern HPC systems, it is necessary to improve power...
With the rapid progress in semiconductor technologies, more and more accelerators can be integrated onto a single SoC chip. In SoCs, accelerators often require deterministic data access. However, as more and more applications are running simultaneous, latency can vary significantly due to contention. To address this problem, we propose a template-based memory access engine (MAE) for accelerators in...
Many countermeasures exist to protect the stack and heap from code injection attacks, however very few countermeasures exist that will specifically protect global and static variables from attack. In this paper we suggest a way of protecting global and static variables from these type of attacks, with negligible performance and memory overheads. Our approach is based on the idea of separating data...
Two of the most significant factors in the success of todaypsilas system-on-chip (SoC) designs are the ability to deliver efficient access to off-chip high speed memory and the ability to be compatible with several different interface-timings of several different sorts of memories. This paper introduces a novel general external memory interface (GEMI) architecture for the high performance and high...
With the development of GPS and wireless techniques, more and more applications require maintaining the current position of moving objects on road network environment. It is the key stone that how to built an efficient index to supporting very high rates of spatial-index updates. Previous works in this domain assume that system holds enough main memory to buffer operations. This specialty enable these...
A geometric programming framework is proposed in this paper to automate exploration of the design space consisting of data reuse (buffering) exploitation and loop-level parallelization, in the context of FPGA-targeted hardware compilation. We expose the dependence between data reuse and data-level parallelization and explore both problems under the on-chip memory constraint for performance-optimal...
In multi-context dynamically reconfigurable processor array (DRPA), the required number of contexts is often increased by those with low resource usage. In order to execute such contexts without wasting a context memory, we propose a new execution mode called instruction buffer mode in addition to the normal multi-context mode. In this mode, a configuration code from the central configuration memory...
Multi-Core Digital Signal Processors (MC-DSPs) often suffer from limited memory bandwidth and long access latency caused by shared-memory structures. Data forwarding is an efficient data speculation technique to hide memory access latencies. This paper proposes a new Data Stream Clustered Forwarding (DSCF) technique for MC-DSPs in shared-memory structures. DSCF combines data streams forwarding operations...
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