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Dedicated hardware accelerators enable energy-efficient implementations of radio and imaging basebands. Multistandard, multi-mode radio basebands require an on-the-fly reconfigurable fast Fourier transform (FFT) accelerator that implements many different FFT sizes. An instance of a runtime-reconfigurable 2n3m5k FFT accelerator was generated by a custom hardware generator to meet the requirements of...
Random numbers are critical in every cryptographic fields. They can be used as cryptographic key, seed, nonce, initialization vector, etc. In this paper, new (pseudo) random number generator (PRNG or RNG) based on computer's source is proposed. The principle of method consist in collecting (nearly) random sources produced from computer and used it as seed for (pseudo) random number generation. Random...
Image compression is of a great importance in multimedia system applications because it drastically reduces bandwidth for transmission and memory storage. Image compression algorithm, like JPEG2000, utilizes the Forward Discrete Wavelet Transform (FDWT) and Inverse Discrete Wavelet Transform (IDWT). The main problems face by researchers in the hardware implementation of the FDWT/IDWT are storage memory,...
In this paper, we present CORT, a factored concolic execution based methodology for high-level functional test generation. Our test generation effort is visualized as the systematic unraveling of the control-flow response of the design over multiple explorations. We begin by transforming the Register Transfer Level (RTL) source for the design into a high-performance C++ compiled functional simulator...
A contourn descriptor generator algorithm implemented in embedded system of new generation to obtain shape characterization of manufactured rigid objects is presented in the paper. Acquisition and processing stages to obtain information about the shape of rigid object by way of a descriptor vector are shown in order to be implemented in a single hardware piece processor embedded system to obtain parallel...
In this paper, we propose a cost-efficient hardware design, coarse and fine rotation (CFR) based FFT twiddle factor generator. It aims to extremely reduce the hardware area, especially for the larger length of FFT-points. Also, our proposed approach is generalized for arbitrary FFT sizes, not limited to the power of 2. In hardware implementation by using TSMC 90-nm CMOS technology, the circuit area...
Recent technological advances allowed the word to construct several wearable products that can capture and process the human body bio-signals. The PPG signal becomes one of the most contenders in heart rate monitoring due to their prominent features, flexibility, effectiveness and low costs. This paper present a novel System of PPG Heart rate calculation based on FPGA, using the Pan and Tompkins as...
This paper reports on the Field-Programmable Gate Array (FPGA) real-time implementation of a vector control scheme, by means of hardware-in-the-loop simulation. This approach will be applied for a PMSM used to propel an electric scooter, preceding its integration in a more complex experimental setup. The emerging need for powerful, flexible system-on-a-chip (SoC) platforms for developing complex drive...
Reed-Solomon code or RS code is widely used for error corrections of data in transmission and storages. However, it is thought of as insecure for direct implementation in code-based cryptography due to plaintext-known attacks. In recent years, McEliece cryptosystem with enhanced public key security by generalized RS code and Goppa code are discussed for hardware implementation. In this work, from...
This paper describes and verifies a method of implementing bit error rate (BER) calculation for FPGA-based physical layer security techniques for Software Defined Radio (SDR). Specifically, we describe an independent source signal processing architecture for an efficient calculation of BER for wireless communication modules across the transmitter and receiver nodes. The source components at the transmitter...
This paper presents experimental results that allow high-performance ports in Zynq microchips to be evaluated taking into account parallel computations and their influence on throughput of FIR filters. All projects are based on Xilinx components. We found that although parallel traffic leads to performance degradation, actual throughput is reduced not very significantly. The results of experiments...
The generation of pseudorandom number sequences can be achieved in a variety of ways, with the most secure methods generally requiring substantial processing to generate. Other pseudorandom number generation (PRNG) methods accept a compromise between processing power and security by mixing two independent, but less secure, PRNG outputs with each other. This paper presents a generalized mixing method...
As the memory and storage hierarchy get deeper and more complex, it is important to have new benchmarks and evaluation tools that allow us to explore the emerging middleware solutions to use this hierarchy. Skel is a tool aimed at automating and refining this process of studying HPC I/O performance. It works by generating application I/O kernel/benchmarks as determined by a domain-specific model....
The voltage balancing of the dc-link capacitors in an electric drive system with five-level neutral-point-clamped converters is investigated in this paper. A properly modified space-vector-modulation technique is utilized in combination with a multilevel dc/dc converter for controlling the capacitor voltages. An advanced algorithm has been developed for reducing the losses of the electric drive system...
There is a growing trend within education establishments to teach electrical power system theory within lectures and back this up with software simulation laboratory sessions. This allows the courses to be taught at a lower cost than if real hardware was implemented. However, the students that are graduating from these programs are missing out on the opportunity to learn about real equipment and issues...
Digital Secret Unknown Cipher (SUC) has been proposed in the last decade targeting to counteract the drawbacks of the traditional analog Physical Unclonable Functions (PUF). The SUCs, as pure-digital units, exhibit consistent operation during the whole digital unit's lifetime. This makes SUCs as PUF alternatives attractive for practical creation of clone-resistant units for a broad spectrum of applications...
An accurate detection of spectrum opportunities is a key factor in governing the efficient spectrum usage in a cognitive radio (CR) system. Energy detection based spectrum sensing has been widely used due to its ease of implementation with lower computational complexity; however, its robustness and performance are highly affected by the noise uncertainty. In the present work, a real time hardware...
This paper describes a load management system for tactical microgrids that improves load balancing across three phases and provides load shedding capability. A single hardware design comprised of solid state relays enables switching of loads to specific phases during operation or, alternatively, shedding the loads to reduce demand. Load shedding can help alleviate overloading of generators and load...
This paper proposes a hardware architecture of the multi-band spectral subtraction method for real-time speech enhancement. The proposed hardware architecture has been implemented on field programmable gate array (FPGA) device using Xilinx system generator (XSG) and Nexys-4 development board. Multi-band approach is based on the fact the whole speech spectrum does not be affected uniformly by the colored...
True Random Number Generators (TRNG) are used in a variety of applications including cryptographic algorithms, communication systems, simulations, etc. From a security perspective, TRNGs are particularly important because they can produce random output bits that are fully unpredictable and unbiased. Random sources are not often apparent and it is useful to have intrinsic hardware-based random number...
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