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This paper presents the Implementation and Comparative Analysis of Double Gate Low Power Multiplexer using Dynamic Logic Styles. The main design goal for VLSI designers is to optimize power. In Conventional CMOS with single gate terminal short channel effects and leakage problems occur. This can be overcomed by moving on to new technological era i.e., Double Gate Technology. Multiplexers are used...
This paper presents a new integrated Lab-On-a-Chip (LOC) based on Differential electric-field sensitive Field-Effect Transistor (DeFET) sensor array that is used in Biomedical Analysis. The proposed system introduces a 4 × 4 DeFET sensor array, analog multiplexer, and readout circuit that perform the sensing, actuating, and signal conditioning tasks. The proposed LOC is verified using circuit level...
Transistor count is the primary concern which affects the design complexity of the circuit. For such submicron CMOS technology area, power dissipation and speed are very important factors for high speed and low power applications. An Asynchronous Parallel Self-timed Adder (PASTA) implemented by using Gate Diffusion Input (GDI) Technique. This advanced technique used to reduce area, power and transistor...
Conventional CMOS technology comes up with a percentage of margins when climbing into a nano-level. So to overcome this, several substitute technologies have been proposed as a solution. Quantum dot Cellular Automata (QCA) technology is one such upcoming nano-technology that can be a perfect substitute of Complementary Metal Oxide Semiconductor (CMOS) due to its low power consumption and high speed...
The Carry Skip Adder (CSKA) is identified by a better efficiency in the trade off between operating speed and power dissipation, as it has a very low power-delay product, near to that of a carry-look ahead adder (CLA). A CSKA consists of blocks of full adder combined together, whose schematic (i.e., combination of full adders per block) mainly affects the overall operating speed of carry skip adder...
Magnetic tunnel junction (MTJ) is one of the spintronic effects and in front of complementary metal oxide semiconductor (CMOS) technology. This element is capable of performing logical calculations and storing the output data in itself, therefore, the day by day use of it makes it more extensive in combination with CMOS as well as its reduction in designing logical, programmable and memory circuits...
Quantum Dot Cellular Automata (QCA) is an emerging and promising technology. When CMOS technology faces serious challenges, the nanotechnology comes into play. QCA overcomes the limitations of CMOS technology and thus capable of replacing the CMOS technology. This article presents a 2 Dot 1 Electron QCA design methodology of reversible 2 : 1 MUX. In our present scope, we concentrate only on the logical...
Feature size of CMOS technology continues to scale down; new devices like FinFET are experimented and proposed as an alternative device due to its superior characteristics. In this paper we have presented low voltage, high speed 1-bit full adder cells in Branch Based Logic and Pass Transistor (BBL-PT) logic by using FinFET model parameters. In BBL-PT full adder lies a drawback i.e. voltage step existed...
From the past few decades, VLSI technologyhas been growing to the large extent. All credit for this goes to the increasing usage of integrated circuits for every embedded system, mobile technologies, computing systems, etc. Increasing growth and use of technology has increased the thirst for low energy or power consumption. An Adiabatic approach is perfect solution for the designing of power and energy...
Circuit designing using CMOS logic is the promising field for VLSI engineers, but with demand of small and portable devices, new techniques for low power are emerging. This paper proposed four different 10-T subtraction logic using Gate Diffusion Index (a new technique for low power design). Simulation results are performed using 180nm technology using Cadence Virtuoso. Complete verification for performance...
This paper presents a design of a 4-bit arithmetic logic unit (ALU) by taking vantage of the concept of gate diffusion input (GDI) technique. ALU is the most crucial and core component of central processing unit as well as of numbers of embedded system and microprocessors. In this, ALU consists of 4x1 multiplexer, 2x1 multiplexer and full adder designed to implements logic operations, such as AND,...
CMOS based technologies fail to satisfy the Moore's law beyond Nano scale, leading to intensive research in identifying an alternative technology that can take over CMOS in the near future. Quantum Dot Cellular Automata (QCA) is one among the various technologies proposed by the International Technology Roadmap for Semiconductors (ITRS) as a viable alternative to CMOS. QCA offers the highest device...
A high-performance 128-input CMOS multiplexer (MUX) tree is designed in this study. In order to enhance the speed, the high-speed feature of traditional transmission-gate MUX circuits and CMOS MUX circuits are integrated to the 128-to-1 MUX tree with high transmission speed. The circuit simulation in the CMOS 0.18μm process presents 26% reduction of delay time, comparing to the 128-to-1 MUX tree composed...
This paper presents a half-run RC5 cipher architecture with low power dissipation for transmission security of biomedical systems. The proposed architecture uses a resource-sharing approach utilizing only one adder/subtractor, one bi-directional barrel shifter, and one XOR with 32-bit bus width. Therefore, two data paths are switched through four multiplexers in the encryption/decryption procedure...
This paper presents a phase modulator topology suitable for frequencies up to 3 GHz. The proposed phase modulator offers digital phase modulation for digital centric polar transmitter frontends as used e.g. in software defined radios. The achievable phase resolution is 11.2° which equals 10.4 ps at 3 GHz. The phase modulation is based on an delay lock loop (DLL), from which signals with different...
Efficient addition of binary numbers plays a very important role in the design of dedicated as well as general purpose processors for the implementation of arithmetic and logic units, branch decision, and floating-point operations, address generations, etc. Several methods have been reported in the literature for the fast and hardware-efficient realization of binary additions. Among these methods,...
Digital IC designers often use SRAM macrocells to implement on-chip memory functionality. In this paper we argue that in several situations, standard cell based memories (SCMs) can have advantages over SRAM macrocells. Various ways to implement SCMs are presented and compared to each other for different CMOS technologies and standard cell libraries and to corresponding macrocells, aiming for finding...
Advance Encryption Standard (AES), has received significant interest over the past decade due to its performance and security level. In this paper, we propose a compact 8-bit AES crypto-processor for area constrained and low power applications where both encryption and decryption is needed. The cycle count of the design is the least among previously reported 8-bit AES architectures and the throughput...
This paper presents a new technique which combines variable-threshold (VT) keeper with split-domino (SD) logic technique to improve the power performance. The proposed technique yields 9-14% energy reduction, with 10% area overhead. We will compare the proposed method with the-state-of-the art for reducing leakage current in domino logic circuits. A 16-bit multiplexer circuit, in 0.13 mum CMOS technology...
In this paper, we compare different existing keeper techniques for reducing power consumption of wide domino logic circuits. We will compare power consumption plus area overhead of each of these methods, with the conventional keeper circuit. A 16-bit multiplexer circuit, in 0.13 mum CMOS technology operating at a frequency of 500 MHz is our test-bench. Simulations show split-domino (SD), with 53%...
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