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With the fast increasingly use of image and video processing in many aspects, the requirements for high performance and high-quality systems lead to the use of reconfigurable computing to accelerate traditional image processing platforms. In this work, an efficient runtime adaptable floating-point Gaussian filtering core is proposed to achieve not only high performance and quality but also kernel...
Data centers availability is mandatory and is conditioned by a quick response to failures and attacks thanks to efficient live forensics. However, this task is lately impossible to complete with classic systems because of encountered data rates and service diversity. Moreover, Software-Defined Networking (SDN) devices agility requirements prevent the use of Application Specific Integrated Circuits...
Implementing self-adaptive embedded systems, such as UV, involves an offline provisioning of the several implementations of the embedded functionalities with different characteristics in resource usage and performance in order for the system to dynamically adapt itself under uncertainties. FPGA-based architectures offer for support for high flexibility with dynamic reconfiguration features. We propose...
As the power wall has become one of the main limiting factors for the performance of general purpose processors, the trend in High Performance Computing (HPC) is moving towards application-specific accelerators in order to meet the stringent performance requirements for exascale computing while still satisfying power budget constraints. Within this context, reconfigurable devices, and more specifically...
One of the key challenges facing genomics today is how to efficiently analyze the massive amounts of data produced by next-generation sequencing platforms. With general-purpose computing systems struggling to address this challenge, specialized processors such as the Field-Programmable Gate Array (FPGA) are receiving growing interest. The means by which to leverage this technology for accelerating...
This paper proposes a generic hardware architecture for runtime acceleration of heterogeneous high performance computing (HPC) clusters. This runtime accelerator performs real time resource allocation and management of HPC systems with low latency on multiple time scales. One of the target applications is to perform the signal processing in wireless communication systems such as LTE and 5G over the...
Reconfigurable datapaths can be used to implement multiple applications on the same hardware. Switching between applications can be realized by loading new configuration information into the datapath. In this contribution, we want to use such datapaths for high frequency event processing. We have developed the toolset ReEP, which takes multiple problem descriptions and superposes them into one reconfigurable...
In the field of high performance heterogeneous computing systems, field programmable gate arrays (FPGAs) have shown great advantages in terms of acceleration and energy efficiency. And with the inclusion of the OpenCL framework for parallel programming, the design complexity has been greatly reduced. However, the parallel implementation of applications containing data-dependent branches usually experiences...
The use of reconfigurable chips such as FPGAs in embedded systems for many runtime applications is limited by large reconfiguration time. Techniques to circumvent this limitation relies on hardware task reuse which preserve certain circuits on the chip. However, the frequent addition and removal of circuits while preserving others on the chip will inevitably lead to fragmentation of its area, in an...
Library based design and IP reuse have been previouslyproposed to speed up the synthesis for large-scale FPGAdesigns. However, previous library based design flow faces severalunresolved challenges. Firstly, there may result in large wastearea between the modules due to the difference in module sizes. While utilizing multiple ratio modules can help to reduce thewaste area, pre-synthesis each module...
Real-time embedded systems are present in various application domains such as automotive, aeronautical, space, and telecommunications. Avionics systems (i.e., aviation electronics) represent a specialized class for the aerospace branch. It is a fact that avionics are getting more and more complex considering functionality and design and also using an increased number of digital computer resources...
EURECA architectures have been proposed as an enhancement to existing FPGAs, to enable cycle-by-cycle reconfiguration. Applications with irregular data accesses, which previously cannot be efficiently supported in hardware, can be efficiently mapped into EURECA architectures. One major challenge to apply the EURECA architectures to practical applications is the intensive design efforts required to...
Heterogeneous System Architectures (HSA) are gaining importance in the High Performance Computing (HPC) domain due to increasing computational requirements coupled with energy consumption concerns, which conventional CPU architectures fail to effectively address. Systems based on Field Programmable Gate Array (FPGA) recently emerged as an effective alternative to Graphical Processing Units (GPUs)...
➔ The incremental step of LiveSynth reduces synthesis time by about 95% for incremental changes. ➔ LiveSynth shifts the paradigm to small, incremental changes and more iterations per day. ➔ We advocate for an interactive synthesis flow as a way to boost design productivity.
Relational databases execute user queries through operator trees, where each operator has a well defined interface and a specific task (e.g., arithmetic function, pattern matching, aggregation, etc.). Hardware acceleration of compute intensive operators is a promising prospect but it comes with challenges. Databases execute tens of thousands of different queries per second. Thus, if only one specific...
In order to reach exascale performance, current HPC systems need to be improved. Simple hardware scaling is not a feasible solution due to the increasing utility costs and power consumption limitations. Apart from improvements in implementation technology, what is needed is to refine the HPC application development flow as well as the system architecture of future HPC systems. ECOSCALE tackles these...
This paper presents a generic hardware design which allows the composition of application specific datapaths at runtime. The architectural template consists of a grid of identical tiles which are connected by a lightweight network-onchip. A processor core is used to configure pre-synthesized basic processing elements to arbitrary tiles at runtime. The sum of these personalized processing elements...
Nowadays, we are witnessing trends in technology, fabrication processes and computing architectures that lead to the design and development of processing systems constituted by a relevant number of independent, heterogeneous execution resources. The aim is to achieve high-performance while leveraging on other aspects, such as energy consumption. Indeed, heterogeneity comes at the cost of greater design...
Dynamically adaptive systems respond to environmental conditions by modifying their processing at runtime, selecting alternative configurations of computation. While FPGAs with partial reconfiguration (PR) seem to offer an ideal platform for flexible hardware, designing such systems is difficult, and no standardised model and methodology exists. We present CoPR, a fully automated framework for implementing...
Feature selection in pattern recognition is a problem whose space complexity grows exponentially regarding the number of attributes in a dataset. There are several hardware implementations of algorithms for overcoming this complexity. These hardware architectures relay on a software component for filtering irreducible features subsets, which is a computationally complex task. In this paper, a new...
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