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This paper addresses the security issues of data transmitted in the backward channel of networked control systems (NCSs) under deception attacks, especially confidentiality and integrity. As a kind of typical active attacks, deception attacks can severely degrade the system performance or even destabilize the system. To detect the deception attacks on the backward channel of NCSs, a detection scheme...
In this paper, an efficient method for high speed hardware implementation of AES algorithm is presented. So far, many implementations of AES have been proposed, for various goals that effect the SubByte transformation in various ways. These methods of implementation are based on combinational logic and are done in polynomial bases. In the proposed architecture, it is done by using composite field...
In this paper, compact architectures for AES Mix Column and its inverse is presented to reduce the area cost in resulting AES implementation. In the hardware implementation of AES with direct mapping substitute byte optimization, MixColumn/Inverse MixColumn transformation demands the utilization of logic resources and then effects the critical path delay and resulting throughput. The proposed MixColumn/Inverse...
Cryptographic algorithms such as International Data Encryption Algorithm(IDEA) have found various applications in secure transmission of the data in networked instrumentation and distributed measurement systems. Modulo 2n +1 multiplier and squarer play a pivotal role in the implementation of such crypto-algorithms. In this work, an efficient hardware design of the IDEA (International Data Encryption...
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