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Self-heating and substrate effects are discussed and qualitatively compared in the ultra-thin body ultra-thin BOX (UTB2) devices without a ground plane. Ultra-thin body is aggravating thermal properties of the devices due to the interface effects. Ultra-thin BOX (10 nm) improves heat dissipation from the channel to the bulk silicon substrate but also results in strongly pronounced substrate effects...
In this work, we use scanning tunneling microscopy (STM) to study the localized degradation, breakdown and post-breakdown of a high-κ (HK) gate dielectric material, cerium oxide (CeO2) deposited directly on a silicon substrate. The novelty of the study lies in analyzing the breakdown phenomenon from a macroscopic metal-oxide-semiconductor (MOS) capacitor level to a very localized nanoscale breakdown...
In this letter, hole mobility characteristics in Si gate-all-around nanowires on (110)-oriented silicon-on-insulator substrate have been studied, based on the advanced split C-V method. Fabricated nanowires have rectangular shape, and the height is fixed to 18 nm. High hole mobility in [110]-directed nanowires (widths ranging from 25 to 68 nm) were observed, illustrating 2.4 X enhancements over the...
For the first time, the performance impact of (110) silicon substrates on high-k + metal gate strained 45 nm node NMOS and PMOS devices is presented. Record PMOS drive currents of 1.2 mA/um at 1.0 V and 100 nA/um Ioff are reported. It will be demonstrated that 2D short channel effects strongly mitigate the negative impact of (110) substrates on NMOS performance. Narrow width (110) device performance...
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
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