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A fully integrated RF CMOS front-end (FE) IC (FEIC), which is fabricated with a 0.13-$\mu\text{m}$ bulk RF CMOS process for wireless local area network/Bluetooth (WLAN/BT) applications, is presented. The proposed FEIC includes a dual-mode power amplifier (PA), integrated switches, and a shared low-noise amplifier (LNA) without external matching networks. The proposed compact reconfigurable matching...
This paper describes the design of mm-wave integrated transformers and their application within a power amplifier (PA) in a 28 nm CMOS technology. The PA presents a 2-stage common-source differential topology and employs one transformer at the input and another at the output to perform single-ended to differential conversion, as well as another transformer to perform interstage matching. The baluns...
This paper presents a novel unbalanced transformerless vector-sum phase shifter architecture. The proposed approach is based on the forming of four signals from the input unbalanced signal by an RC quadrature all-pass filter. These signals are subtracted to obtain a pair of orthogonal signals which are added on the load network of the Gilbert cells with weighted coefficients to form the differential...
This paper presents the simulation results of a linear, fully integrated, two-stage digitally programmable 130 nm CMOS power amplifier (PA) operating at 2.4 GHz. Its power stage is composed of a set of amplifying cells which can be enabled or disabled independently by a digital control circuit. All seven operational modes are univocal in terms of 1 dB output compression point (OCP1dB), saturated output...
A fully-integrated ultra-wideband power amplifier (PA) for multi-mode multi-band applications is designed and implemented in a standard 0.25 μm Ultra-CMOS Silicon-on-Sapphire (SOS) technology. The PA consists of two series stacked Cascode configuration to achieve high output power while maintaining stability. The PA utilizes stacked transistor switches at the input to extend the operation bandwidth...
Integrated circuit researches in KAIST in the area of digital polar CMOS power amplifiers (DPAs) are presented, which include a high dynamic range DPA, and a dual-power-mode output matching network for a DPA to improve low power efficiency. The high dynamic range DPA introduces the sub-amplifier cell array with LO leakage canceller to improve local oscillator (LO) leakage and a digitally controlled...
A two-stage mm-wave power amplifier (PA) is presented. Designed in a 65 nm CMOS process, the PA employs capacitive neutralization in each stage for increased differential isolation and gain. Baluns are used for single-ended input/output signal to balanced signal conversion, and the interstage matching consists of a 2:1 transformer. With a 1.2 V supply, at 67 GHz, measurements show a gain of 16.8 dB,...
This paper presents a fully integrated IF module which can receive or transmit signal with only one port. The switching time between reception and transmission is less than 3µs. In the state of reception, the IF module can convert differential signal to single-ended signal. Simulation results show 3.2dB power gain and 11.65dBm OP1dB while drawing 45mA from a 3.3V supply. In the state of transmission,...
An Radio Frequency (RF) Power Amplifier (PA) plays a key role in front end of RF Transmitter. It's role is to convert low power RF Signal into high Power signal so that it can drive the antenna of the transmitter. The PA exhibits certain desirable characteristics such as enormous output Power, reduced heat dissipation, nominal input and output return loss and eminent gain. It is necessary to cut down...
This paper demonstrates a CMOS digital polar transmitter with flip-chip interconnection to low-temperature co-fired ceramic (LTCC) interposers. The LTCC interposers contain the PA output balun targeting different operating frequency bands, and the reconfiguration in the carrier frequency is achieved by selecting an appropriate LTCC interposer. The same CMOS core transmitter is reused for different...
The millimeter-wave differential power amplifier using on-chip transformer is proposed to achieve high saturated power. To realize the high freqency operation, cross couple capatitor MOSFET is applied. The parasitic element is reduce the performance of the circuit. In this paper on-chip transformer is used as balun and impedance-matching network. The component loss is reduced by unifying the function...
A simplified output matching network for pulse width modulated Class-E Power Amplifier for efficiency enhancement at back-off power level is proposed. The shunt capacitance and the series inductance in the Class-E PA are realized through capacitor banks that are tuned according to the duty cycle to meet ZVS conditions. The differential PA design is implemented in 130 nm CMOS technology achieving maximum...
In this paper, a detailed methodology for designing a low-power high-efficiency power amplifier (PA) is presented. The trade-off between high efficiency and low output power is highlighted. An example is described to validate the proposed design method. Simulated peak efficiency up to 50.3% has been achieved with all components on-chip. Furthermore, a tunable power amplifier with efficiency enhanced...
This paper presents the design of a wideband class AB cascode Power Amplifier (PA) using UMC 0.18µm CMOS process for UWB applications covering lower band of 3–5 GHz. Designed class AB PA delivers an output power of 1.80267 dBm at an input 1-dB compression point of −11.144 dBm for a 4 GHz frequency. It achieves a good gain flatness of 13.3±1.0 dB over the entire 3–5 GHz. The matching networks are designed...
A high-gain, Q-band power amplifier (PA) implemented in 45-nm silicon-on-insulator (SOI) CMOS is presented. The PA is designed for fully integrated radios and provides 30.7 dB of gain to allow the digital baseband to fully saturate the PA at 18.7 dBm output power. This is achieved with an overall power-added efficiency (PAE), including all pre-driver and impedance matching networks, of 18.1%. The...
In this paper, a three-stage power amplifier (PA) designed for V-band applications is presented. The proposed PA adopts common-source topology for each stage and is implemented in the CMOS 90-nm process technology. This V-band PA achieves a small signal gain of 11.9dB and a saturated output power of 7.6dBm at the 60GHz operating frequency. The measured peak power added efficiency (PAE) is 4.77%, and...
This paper presents the design of a 2.4-GHz CMOS Class E power amplifier (PA) for wireless applications in Silterra 0.13-µm CMOS technology. The Class E PA proposed in this paper is a single-stage PA in a cascode topology in order to minimize the device stress problem. All transistors are arranged in parallel to decrease on-resistance for high efficiency with on-chip input and output impedance matching...
In this paper, a two-stage cascode class F power amplifier (PA) intended for class 1 Bluetooth application is presented using standard 0.18-μm CMOS technology. In the proposed PA, a cascode schematic is used not only to avoid from overflow current but also to have a good isolation. Furthermore, the class F power amplifier is designed to improve the power efficiency using the operating mode in either...
A novel high efficiency, large output-power, 2-bit tuned mm-wave DAC realized in 45-nm SOI CMOS is demonstrated. A record breaking 24.3 dBm output power is achieved at 45 GHz with 18.3 dB saturated gain, >14.5 Vpp differential output swing, a drain efficiency of 21.3% and 14.6% PAE. The best PAE is 22% at an output power of 23.5 dBm. Operation at 45 GHz with up to 2.5 Gbps BPSK and up to 1.25 Gbps...
Millimeter-wave Distributed Active Transformer (DAT), baluns and zero degree 1–4 splitter have been optimized to design a 60 GHz parallel Power Amplifier (PA). The implementation is based on a thin digital 7 metal layers (1P7M) Back End of Line (BEOL) and Low Power (LP) transistors in 65 nm CMOS technology from STMicroelectronics. A lumped model based analysis is presented to compare pure voltage...
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