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SPICE is the de facto standard for circuit simulation. However, accurate SPICE simulations of today’s sub-micron circuits can often take days or weeks on conventional processors. A SPICE simulation is an iterative process that consists of two phases per iteration: model evaluation followed by a matrix solution. The model evaluation phase has been found to be easily parallelizable, unlike the subsequent...
Space-Time Adaptive Processing (STAP) technique can restrain the effects of interference and clutter effectively. However, the calculation of STAP weights, including QR decomposition (QRD) and solving linear equations needs intensive computation. This paper mainly focuses on improving the QRD algorithm and presents an efficient FPGA design, based on floating point IP core, which can meet the requirement...
Auto white balancing is the process of keeping the color of objects constant automatically under different illumination conditions by calculating a number of parameters from the image data. These parameters are used to change the image pixel values to keep the color constant. This paper discusses the Lam's auto white balance algorithm and presents a novel, high-performance and cost-effective implementation...
The problem of finding efficiently the first k minimum or maximum values is generally met in many application fields, such as error control coding. More specifically, optimized solutions for the selection of the two or three smallest elements out of a given set of numbers are greatly needed for the design of high-speed Low-Density Parity-Check (LDPC) decoders, as this min-search can be the bottleneck...
This paper discusses the implementation of math hardware module based on CORDIC algorithm to solve trigonometry, hyperbolic and exponential function on FPGA. CORDIC is one of the hardware efficient and iteration based algorithms that is used to implement various transcendental functions such as trigonometry, hyperbolic, exponential and so forth. In addition, by using this algorithm, the hardware requirement...
This paper presents direct implementation of parallel Particle Swarm Optimization (PSO) algorithm on Field Programmable Gate Array (FPGA). In the proposed design, the particle unit architecture is independent of fitness unit and hence the particle unit is reusable and flexible for different fitness function. The parallel co-processor implementation of each particle accelerates the execution speed...
Cholesky decomposition has wide applications in solving many engineering and scientific problems. Acceleration is an important issue in many of these problems. In this paper, a hardware-based LLT Cholesky decomposition featuring high throughput has been presented to solve wiener filtering based on the minimum square error criterion. To achieve the best efficiency, the hardware-based implementation...
Traditionally, microprocessor and digital signal processors have been used extensively in controlling simple processes, such as direct current motors. The Field Programmable Gate Arrays (FPGA) are currently emerging as an alternative to the previously used devices in controlling all sorts of processes. The fractional order proportional-integrative control algorithm has the advantage of enhancing the...
Model Predictive Control (MPC) is based on the idea to produce control input as a solution to real-time optimization problem. The advantage of MPC is that MPC can works effectively within constraints of the real actuator which are relatively narrow. The disadvantage of MPC lies on its complex algorithm that needs longer time than the other controller. This paper discuss the MPC application for TITO...
A field programmable gate array (FPGA)-based predictive controller for a spacecraft rendezvous manoeuvre is presented. A linear time varying prediction model is used to accommodate elliptical orbits, and a variable prediction horizon is used to facilitate finite time completion of manoeuvres. The resulting constrained optimisation problems are solved using a primal dual interior point algorithm. The...
In this paper a Substitution Permutation Network( SPN) type, symmetric-key block cipher architecture has been proposed to strengthen it against fault attack. The proposed SPN type architechture employes two different types of diffusion layers. Each odd round contains eight parallel 16 bits diffusion layer and each even round contains two parallel 64 bits diffusion layer. Our architecture has been...
In the paper, a novel implementation technique of orthogonal FIR systems is proposed. Starting from a state-space model of such a system, presented algorithm computes a fully pipeline structure consisting of Givens Rotations. This technique is illustrated by an FPGA hardware design example of a low-pass FIR filter.
Coordinate Rotation Digital Computer (CORDIC) based digital signal processing has become an important tool in communications, biomedical and industrial products, providing designers with significant impetus for making algorithm into architecture. In this paper, a new kind of CORDIC algorithm was presented which was based on the state machine structure and iterative operation of multilevel pipeline...
Increasing calculation speed without affecting pixel calculation accuracy in fast image processing algorithms using parallel computation was always needed but controlled by Amdahl's Law. In fact increasing number of processors uses same data bus reduces the speed and not allowing us to get the 20 times faster as we expected. As number of processors are limited due to sharing processors same data bus...
High level synthesis using C/C++ code of applications is rapidly gaining ground. However, support for calculations is restricted to elementary algebraic operations of addition, multiplication, subtraction and division. Support for transcendental functions is generally unavailable and is inefficient where available. Transcendental functions are an important part of high performance computing. A framework...
With the demand of real time rendering of large scale of filed scenes, which require the graphic's processing unit that have the features of high efficiency and low power. the rasterization of graphics is a stage of compute intensive and is a key part to raise the system performance. In this paper, I improve the “CENTROL LINE” rasterization, is the main method for designing VLSI, and focus on the...
This paper proposes an embedded surveillance system for real-time anomaly intrusion detection based on temporal difference algorithm and theft items detection based on accumulated background subtraction algorithm. This design of modified vision algorithm fully utilize the advanced parallelism of Field Programmable Gate Arrays (FPGA) and this hardware implementation realizes time-consumed difference...
A multi-channel image superimposition system is designed in this paper. It can superimpose white-light image on infrared thermal image to generate mixture image. The system is realized on a FPGA chip and is mainly composed of multi-channel DMA controller and image superimposition module. Multi-channel DMA controller can realize data exchange between image superimpositon module and memory independent...
In this paper, based on the Xilinx XUP V5-LX110T board, a video post processing platform with a professional HDMI interface circuitry is designed and a novel de-interlacing algorithm is designed, which performs better than the industry leading algorithms as experimental results show. This platform is to verify our HD video post processing SOC chip which is under development.
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