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Cooperation of software and hardware with hybrid architectures, such as Xilinx Zynq SoC combining ARM CPU and FPGA fabric, is a high-performance and low-power platform for accelerating RSA Algorithm. This paper adopts the none-subtraction Montgomery algorithm and the Chinese Remainder Theorem (CRT) to implement high-speed RSA processors, and deploys a 48-node cluster infrastructure based on Zynq SoC...
In this paper, the implementation of the K-means clustering algorithm on a Hadoop cluster with FPGA-based hardware accelerators is presented. The proposed design follows MapReduce programming model and uses Hadoop distribution file system (HDFS) for storing large dataset. The proposed FPGA-based hardware accelerator for speed up the K-means clustering algorithm is implemented on Xilinx VC707 evaluation...
Frequent itemset mining is a fundamental step in analysis of big data where correlation among the raw data in deemed necessary. In modern era the amount of data available for processing has grown exponentially, making it a stepper task for mining algorithms to provide solution in a timely manner. The software implementations are normally not efficient in handling such datasets thus focus on parallel...
With recent advances in Field Programmable Gate Array (FPGA) architecture and design, the robustness and scalability of design implementation tools is becoming increasingly important. In an FPGA implementation flow, the basic logic elements (BLEs) like flip-flops (FFs) and lookup tables (LUTs) are clustered into adaptive logic modules (ALMs) and Logic Array Blocks (LABs). Clustering is a key stage...
Cardiovascular system is the most important part of human body which has role as distribution system of Oxygen and body's wastes. To do the job, there are more than 60.000 miles of blood vessels participated which can caused a problem if one of them are being clogged. Unfortunately, the conditions of clogged blood vessels or diseases caused by cardiovascular malfunction could not be detected in a...
In this paper, a new architecture for accelerating homomorphic function evaluation on FPGA is proposed. The architecture is based on a parallel cached NTT algorithm with an overall time complexity O(√N log √N). The architecture has been implemented on Xilinx Virtex 7 XC7V1140T FPGA that achieves a 60% utilization ratio. The implementation performs 32-bit 216-point NTT algorithm in 23.8μs which is...
In this paper, a configurable many-core hardware/software architecture is proposed to efficiently execute the widely known and commonly used K-means clustering algorithm. A prototype was designed and implemented on a Xilinx Zynq-7000 All Programmable SoC. A single core configured with the slowest configuration achieves a 10× speed-up compared to the software only solution. The system is fully scalable...
The high flexibility of FPGAs predestines them for emulation and prototyping of ASICs. Despite the progress in VLSI technology, high performance FPGAs can be very cost intensive. To reduce these costs, we propose a scalable cluster of low cost mainstream FPGA boards. This paper presents a new approach for the distribution of application tasks into a cluster of FPGAs. The algorithm is split up into...
As FPGA architecture evolves, complex heterogenous blocks, such as RAMs and DSPs, are widely used to effectively implement various circuit applications. These complex blocks often consist of datapath-intensive circuits, which are not adequately addressed in existing packing and placement algorithms. Besides, scalability has become a first-order metric for modern FPGA design, mainly due to the dramatically...
This paper present a novel architecture for image segmentation. The design is based on the fuzzy c-means algorithm based gaussian function in pulse mode for reducing the large storage requirement. The proposed algorithm is tested in mammogram image segmentation approximately with 0.92 of segmentation index. The pulse mode stochastic computing technique is implemented with a simple bloc avoiding the...
Field Programmable Gate Arrays (FPGAs) CAD flow run-time has increased due to the rapid growth in size of designs and FPGAs. Researchers are trying to find new ways to improve compilation time without degrading design performance. In this paper, we present a novel approach that identifies tightly grouped FPGA logic blocks and then uses this information during circuit placement. Our approach is an...
Adaptive logic module (ALM) in modern field programmable gate array can serve as one 6-input lookup table (LUT) or two smaller lookup tables under certain constraints. In a typical design flow, a netlist of LUTs formed after technology mapping has to be merged into ALMs and then packed into coarse-grained logic blocks (CLBs) before placement and routing. How the LUTs are merged and the ALMs are packed...
Supergenes are an addition to a genetic algorithm's genome that duplicate genes in the genome, represent local optimizations, and have the potential to be expressed overriding the duplicated gene. We introduce supergenes in a genetic algorithm for FPGA placement where a placement algorithm places a mix of fine-grain components and medium-grain components (where a medium-grain component is 2 to 10...
A low noise, high speed board designed for drift chamber signals processing has been developed. The Front End electronics is a multistage amplifier based on high performance commercial devices. In addition, a fast readout algorithm for Cluster Counting and Timing purposes has been implemented on a Xilinx-Virtex 4 core FPGA. The algorithm analyzes and stores data coming from a Helium based drift cell...
The mean-shift algorithm provides a unique non-parametric and unsupervised clustering solution to image segmentation and has a proven record of very good performance for a wide variety of input images. It is essential to image processing because it provides the initial and vital steps to numerous object recognition and tracking applications. However, image segmentation using mean-shift clustering...
This paper presents a high speed configurable FPGA architecture for k-means clustering. The proposed architecture is highly pipelined, parallel and fully configurable. It can achieve an operating frequency of 400 MHz, which is at least three times faster than prior works. The proposed architecture addresses the high speed and throughput requirements of machine vision, multi-media and data mining applications.
Computationally intensive problems can be represented with data-flow graphs and automatically transformed to locally controlled floating-point units via partitioning. In theory the lack of global control signals enables high performance implementation however placing and routing of the partitioned circuits are not trivial. In practice to create a high performance implementation the clusters should...
Wireless Sensor Networks are gaining importance in diverse applications. The sensor nodes are battery operated and hence energy aware architecture is considered for increasing the lifetime of the sensor network. In this paper clustering algorithm based on spatial correlation is implemented to improve the performance of Distributed Source Coding (DSC) Algorithm. Results show that the proposed clustering...
This paper addresses the design of the mapping tool used for the FPGA application implementation in our SRAM-based FPGAs fabricated in a 0.5 micron SOI-CMOS process. Comparing with the existing mapping tools from academia, we propose several techniques of packing and clustering to improve the technology mapping. The proposed algorithms provide a closer matching of the user logic netlist with the underlining...
FSM-based and microcode-based controllers are two widely known techniques used for memory built-in self test (MBIST). FSM-based controller is commonly the hardwired BIST whilst microcode-based controller is a programmable memory BIST (P-MBIST) controller. The P-MBIST is popular because of their flexibility of programming new test algorithms. Recently, the FSM-based memory BIST has evolved from hardwired...
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