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In this paper, a low-cost accelerator for the ηT pairing in characteristic three over the super-singular elliptic curves is designed. As the critical operations of ηT pairing, the cubing and sparse multiplications over GF(36m) in the Miller's algorithm are merged and their arithmetic are modified and scheduled to reduce the intermediate data related overhead. With these optimizations, the Miller's...
Large number multiplication has always been an essential operation in cryptographic algorithms. In this paper, we propose Broken-Karatsuba multiplication by applying the non-least-positive form to represent large numbers and dig the parallelism hidden in conventional Karatsuba multiplication. Further, we modify Montgomery modular multiplication algorithm with Broken-Karatsuba multiplication to make...
The benefits of customising the precision throughout an FPGA design according to a design tolerance are well known. However, customising the precision of a design at runtime has the potential for an even greater performance impact. In this paper, we add the ability to dynamically choose the internal precision of a datapath. This enables a result that is at least as accurate as the worst-case under...
Stencil computations represent a highly recurrent class of algorithms in various high performance computing scenarios. The Streaming Stencil Time-step (SST) architecture is a recent implementation of stencil computations on Field Programmable Gate Array (FPGA). In this paper, we propose an automated framework for SST-based architectures capable of achieving the maximum performance level for a given...
Hash functions represent a fundamental building block of many network security protocols. The SHA-3 hashing algorithm is the most recently developed hash function, and the most secure. Implementation of the SHA-3 hashing algorithm in Hardware Description Language (HDL) is time demanding and tedious to debug. On the other hand, High-Level Synthesis (HLS) tools offer potential solutions to the hardware...
Triple Modular Redundancy (TMR) is the most widely used technique to increase the reliability of SRAM-based FPGAs. In this paper, we investigate the application of TMR directly in C language-based algorithms to be synthesized using High Level Synthesis (HLS) to generate hardened Register Transfer Level (RTL) designs. We analyze four different TMR designs implemented into a 28 nm SRAM-based FPGA from...
The paper presents an efficient parallel timing synchronization algorithm structure, which is suitable for high speed communications demodulation system and easy to implement on FPGA platform. First, a new parallel timing synchronization structure is displayed. Wherein the proposed parallel structure make up of a feedback loop based on the farrow interpolation filter, Gardner algorithm and the numerically...
The recent rise of image processing circuits all along with the persistent quest for higher levels of performance have enormously contributed to the need of creating more efficient types of image processing circuit. For that, we have proposed a new design that offers us not only a less consuming circuit but also a faster one. Our new design has been tested and has given an interesting gain in power...
Self-mixing interferometry (SMI) has been widely used for sensing of diverse vibration, velocity, displacement, biomedical and flow applications. The simplicity of the SMI configuration enables the design of a low-cost, self-aligned and compact sensor with a small optical component count. SMI occurs when a small portion of emitted coherent optical beam is backscattered by the remote target and re-enters...
This paper describes the design and development of modified CRC algorithm for the hardware implementation on FPGA to meet the speed constraint for Ethernet, using the reduced lookup table algorithm. This algorithm can be applied for any length of data, by processing it in a block of 16 bytes at a time. The last block may have less than 16 bytes. To process an input block of 16 bytes, the algorithm...
In this work, comparative analysis of Booth and Wallace Tree multiplier architectures is presented using Altera small commercial FPGA devices. Comparison is done with respect to resources consumed and maximum frequency achieved for different multiplier bit width. The synthesis results show tradeoff that Booth multiplier offers better performance at the cost of more chip area. This is very useful to...
SAT is one of the most important basic problems of many areas of computer science and control science. SAT solvers are software or hardware to solve an SAT instance. In this paper, an instance-specified SAT solver was developed with FPGA, which implements the DPLL algorithm with our innovative random variable selection. Moreover, we also introduced an innovative tool-chain of our SAT solver, which...
A data acquisition system (DAQ) is an electronic system that collects, stores and distributes information for further processing. This paper put together various DDR techniques for synchronized digital data acquisition algorithms and realization with Field Programmable Gate Array (FPGA). The proposed techniques uses Double data rate for high speed data acquisition where data capturing device is source...
In elliptic curve algorithm, point multiplication is the most core part. Its efficiency determines the execution efficiency of the algorithm. RFID label belongs to resource-constrained device, and it has strict requirement to hardware resource occupied by algorithm execution. Combined with the characteristics of RFID device, the paper modifies modular multiplication, modular inverse algorithm and...
In this work, we have done power analysis of Data Encryption Standard (DES) algorithm using Xilinx ISE software development kit. We have analyzed the amount of power utilized by selective components on board i.e., FPGA Artix-7, where DES algorithm is implemented. The components taken into consideration are clock power, logic power, signals power, IOs power, leakage power and supply power (dynamic...
Deoxyribonucleic Acid (DNA) sequence alignment is essentially a way of comparing two or more DNA sequences with aim to find regions of similarities among them. The Smith-Waterman (SW) algorithm is a local alignment algorithm which is able to identify mutation in DNA sequences. However, the aforementioned algorithm tends to be slower in computation of long DNA sequences. Over decades ago, Field Programmable...
This paper describes digit-by-digit integer restoring and non-restoring algorithms for computing the cube root of a 33-bit radicand and gives improved methods for the implementations of the algorithms to speed up the computations. The methods include calculating multiplication products in advance with additions and using carry save adders (CSAs) to calculate the partial remainder at each iteration...
Radio Frequency Identification (RFID) has been widely used in many areas, but security issues still remain. To overcome these issues, RFID authentication protocols based on cryptographic algorithms have been developed. These protocols require implementing cryptographic components on the tag. In this paper, we focus on the lightweight stream ciphers and the lightweight hash functions that are vastly...
This paper presents a fast compressive sensing reconstruction algorithm implemented on FPGA using Orthogonal Matching Pursuit (OMP). The algorithm is optimized with QR decomposition to solve the least square problem and avoids the square root operations to facilitate the hardware implementation. The implementation results show that this design can run at a frequency of 100MHz and the proposed algorithm...
High-level synthesis for FPGA designs (FPGA-HLS) is recently required in various applications. Since wire delays are becoming a design bottleneck in FPGA, we need to handle interconnection delays and clock skews in FPGA-HLS flow. In this paper, we propose an FPGA-HLS algorithm optimizing critical path with interconnection-delay and clock-skew consideration. By utilizing HDR architecture, we floorplan...
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