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Information-theoretic cost functions such as minimization of the error entropy (MEE) can extract more structure from the error signal, yielding better results in many realistic problems. However, adaptive filters (AFs) using MEE methods are more computationally intensive when compared to conventional, mean-squared error (MSE) methods employed in the well-known, least mean squares (LMS) algorithm....
To solve the non-uniformity problem of multi Time Delay Integral Charge Couple Device (TDICCD) mosaic camera, a non-uniformity correction algorithm is proposed and implemented on Field-Programmable Gate Array (FPGA) platform. Firstly, the generation and definition of non-uniformity are introduced; several common non-uniformity correction methods are discussed. Secondly, the correction algorithm is...
With the improvement of the performance of ADC, it is available to sample and process real signal in intermediate frequency in radio communication system design. The large source usage and long latency of image-reject filter and decimation in IF DDC are the difficult problems in design. But In many occasions the signal can be processed as narrow band signal. In this paper, we designed an M-points...
A higher level, for the Nios II soft processor realizes the IFF encryption authentication technology is discussed in this paper. Through configuration Secure Hash Algorithm (SHA-1) on the Nios II soft processor within Altera FPGA, and communication with the secure EEPROM, an Identification Friend or Foe is completed. This method can provide secure IP protection and license management solution for...
Multi-parallel architecture for MD5 (Message-Digest Algorithm 5) implemented on FPGA (Field-Programmable Gate Array) is presented in this paper. To accelerate the speed, a general architecture for Host Computer and FPGAs is proposed. The MD5 implementation is presented. Besides the internal parallelization of MD5 modules, FPGAs can be easily duplicated and connected to Ethernet LAN. The design was...
Through the research of current digital signal processing, this paper presents a design with FPGA to achieve FFT, gives the overall implementation framework, and focuses on the design and implementation of the FFT algorithm processing unit, thereby increasing the operation speed of the digital signal processor and reducing the computational complexity.
In this paper, a very high-throughput and area efficient hardware decoder of the binary (23, 12, 7) Golay code is presented. The key feature of this proposed algorithm is fast determination of the error positions through the analysis on the weight of syndromes without large operations of finite fields. Comparing with the algorithm using one syndrome, the proposed algorithm is more suitable for the...
The developing semiconductor technology enables the reconfigurable hardware such as FPGA. Distributed reconfigurable system is a FPGA-based hardware accelerated system with network. Applications can be accelerated as hardware module by FPGA in a distributed system. There are few works about application mapping on distributed reconfigurable system. In this paper an application mapping scheme for reconfigurable...
This paper proposes a way of implementing a deadbeat controller in FPGA. The focus is on the FPGA implementation of the digital controller. The emphasis is on the software tools for design and simulation of FPGA based hardware for control applications. The FPGA is interfaced to the controlled process by means of serial analog to digital converter (ADC) and digital to analog converter (DAC). The hardware...
This paper relates to the research on a dexterous hand prosthesis conducted at the Wroclaw University of Technology. The possibility of aiding the prosthesis control system by utilization of application specific digital circuits is presented. Several exemplary designs, prepared during some of to-date works conducted by authors, have been presented. Discussed solutions are part of a bigger project...
Coordinate rotation digital computer (CORDIC) based digital signal processing has become an important tool in consumer, communications, biomedical, and industrial products, providing designers with significant impetus for porting algorithm into architecture. Unfolded implementations of CORDIC algorithm can achieve low latency for rotation and various functions such as division, multiplication, logarithmic...
This paper presents the designed obstacle avoidance program for mobile robot that incorporates a neuro-fuzzy algorithm using Altera?? Field Programmable Gate Array (FPGA) development DE2 board. The neuro-fuzzy-based-obstacle avoidance program is simulated and implemented on the hardware system using Altera Quartus?? II design software, System-on-programmable-chip (SOPC) Builder, Nios?? II Integrated...
The paper presents a novel methodology to implement resource efficient 64-bit floating point matrix multiplication algorithm using FPGA. Approach uses systolic architecture using four processing element (PE's) that gives tradeoffs between resource utilization and execution time, results in reducing the routing complexity for dense matrix multiplication problems.
The computation of shortest path for a mobile automaton between two points in the plane is considered in this paper. An architecturally-efficient solution based on Dijkstra's algorithm is presented for this problem. Results of implementation in Xilinx FPGA are encouraging: the solution operates at approximately 46 MHz and the implementation for a graph with 64 nodes and 88 edges fits in one XCV3200E-FG1156...
Most reconfigurable processors are not fully controlled by software; they are reconfigured using hardware description languages. By moving the data paths into the processor, the system architect can discard the external control logic, the finite state machines and micro-sequencers. Examples for such a processor are the members of the Stretch family, Software Configurable Processors which have a reconfigurable...
This paper presents a novel parallel pipeline FFT processor especially tailored for Multiband Orthogonal Frequency Division Multiplexing (MB-OFDM) Ultra Wideband (UWB) system, which was defined by ECMA International. The proposed Radix 22 Parallel Pipeline processor, which employs two parallel data path Radix 22 algorithm and single-path delay feedback (SDF) pipeline architecture, is a small-area...
This paper presents the implementation of a tightly coupled hardware architectural enhancement to the Altera FPGA-based Nios II embedded processor. The goal is to accelerate Advanced Encryption Standard (AES) operations in 128, 192 and 256-bits, for application in a high-performance embedded system implementing symmetric key cryptography. The concept is to augment the embedded processor with a new...
Field programmable gate array (FPGA) was a new material programmable logic units in end of the 20th century, FPGA was with some properties such that, large memory of capacities, short delays of time, improvement able & flexibilities etc. On the basis theory of neural fuzzy system of Networks (NFSN), this paper gives a FPGA method of DNMA (Dynamic Numbers Measuring Algorithm) with VCN (Variable...
An optimized method to design and implement digital three-phase phase-locked loop (PLL) based on FPGA is presented in this paper. The PLL fits in electric power system as well as other fields. At first, principle and basic structure of the PLL including phase discriminator, loop filter and voltage controlled oscillator (VCO) are introduced, then these modules are designed in VHDL language with blocking...
FPGA placement algorithms have stricter location constraints compared to normal ASIC placers. For large circuits, designers often start by using a best local solution and iterate until a reasonable global solution is attained, with optimization criteria such as minimum delay, area and power. This paper presents a modified greedy algorithm for placing Xilinx FPGA blocks, specifically designed for large...
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