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In this paper, a new sigma delta modulator based on a multiplexed input topology is proposed to decrease power consumption and size in implantable bio-interfacing systems. An opamp sharing technique is employed in order to process several input sequentially. The proposed sigma delta modulator integrates each input separately and stores the integrated value inside a dedicated capacitor. We show that...
The low cost and high efficiency of quasi-resonant flyback converters have resulted in their wide application as the main circuit topology in power-converters. Because conducted electromagnetic interference (EMI) at low frequency domain of conventional quasi-resonant (QR) flyback converters probably exceeds the EN55022 Class-B of EMI standards, this paper presents novel frequency jittering control...
The modular multilevel converter (MMC) is attractive for medium- or high-power applications because of the advantages of its high modularity, availability, and high power quality. However, reliability is one of the most important issues for MMCs which are made of large number of power electronic submodules (SMs). This paper proposed an effective fault detection and localization method for MMCs. An...
This paper describes a new 2-1 cascaded hybrid sigma delta modulator where the discrete time filter is realized with fully differential current conveyor. The hybrid convertor, which is a combination of an analog integrator and two digital integrators, offers an increased dynamic range, helps make the resulting high-order sigma delta modulator stable and reduce power consumption comparing with discrete...
The development of a digital tool dedicated for the test and the simulation of a reading system for neutron detection is presented. This study takes place in the framework of the I_SMART∗ European project. This system will have to work in harsh environment in terms of temperature and radiations what makes necessary the development of specifications for operation and reliability of the components and...
This paper presents a new circuit realization for multi bit continuous time sigma delta modulator. The converter has been designed in a 0.18 um TSMC technology and achieves a maximum signal-to-noise ratio (SNR) of 70 dB in a 1 MHz bandwidth and dissipates 5mW from a 1.8 V supply when clocked at 100MHz. The convertor has a third-order active-RC loop filter, a 4-bit flash quantizer and errors are corrected...
Robust grid synchronisation of power electronic converters is essential for their use with Distributed Generation Systems. A considerable number of techniques have been proposed to address this issue, but often their performance is not fully validated using a consistent experimental setup. Furthermore, even when experimental validation is used, there is still a lack of rigour in many of the evaluative...
Summary form only given. Switched-mode dc-dc converters are routinely employed in the power supply section of low-power electronic systems, such as biomedical implants, to convert a supply voltage from one voltage level to another voltage level. The switched-mode dc-dc converter employs a modulator to modulate the output pulses. In Pulse Width Modulation (PWM)-based digital modulators, an N-bit counter...
This paper introduced the technical requirements and the realization method of multi-channel data acquisition circuit, proposed some solutions to eliminate channel crosstalk. The design can finish to sampling 32 channel analog signals and convert them based FPGA as a core-logic controller, this device has been successfully applied in a comprehensive telemetry device.
Data transmission between an inverter and a motor is usually ensured through dedicated cables. However, for many applications and especially in aircraft, the weight of the wiring is becoming critical. One possible technique to decrease the number of wires is to implement a power line communication (PLC) on the 3-phase power cable connecting the inverter and the motor. The objective of this paper is...
Repair of injured spinal cords by regeneration therapy remains an elusive goal. In this paper, a system aiming at remote motor function restoration with 3G technology has been presented. This system contains three principle sub-systems: neural signal detecting, communication, and functional electrical stimulation. Functions of each sub-system have been introduced. At the end of this paper, electrical...
Traditional voltage sensing method has already been widely used for the synchronous rectifier. However, the parasitic parameters will cause the false turn-on and early turn-off problem. In this paper, the conception of zero-crossing noise filter is presented. By applying this filter to the synchronous rectifier, the false turn-on and early turnoff problem can be resolved. Only three passive components...
This paper characterized the CM noise generation and coupling mechanism to predict the CM noise in Flyback converter. The spectrum of noise sources are analyzed using bandwidth-effects-FFT and the CM noise coupling paths are identified to build up a new CM noise analysis method. With this CM noise analysis method, the total CM noise and the contributions of all the coupling paths in the converter...
This paper presents an exhaustive study of the topology of passive components based on a two-stage single-phase (1Φ) ac-dc converter for a DC nanogrid application. The design of passive components is discussed by considering the aspects of power density, power quality, conducted EMI, dc small-signal interaction, grounding scheme and the common-mode (CM) voltage level. The first-stage ac differential-mode...
AC-DC converters for low power applications have their unique EMI characteristics compared to the converter for other applications. It has very high DM noise due to the DCM or CRM operation and results in a relatively high transformed CM noise caused by the unbalance of the noise propagation paths. This paper summarized the important unbalanced paths and proposed methods to limit the CM noise caused...
Signal integrity and associated optimization techniques in power delivery network for multi-core processors, whether powered by a single converter or several power converters, are discussed. The high integration of the multi-core processors on a single die makes chipset's sensitivity to crosstalk noise more likely. Several power converters in a multi-core processor system could improve energy efficiency...
We propose a new digital algorithm that can shape element mismatch and ISI errors simultaneously. This method fully shapes ISI and the mismatch errors outside audio band and eliminates the need for layout critical and non-automat ed analog design methods that often require multiple design iterations and are hard to migrate over processes. This is enabled by using digital processing circuits that are...
After the first-ever all-digital PLL (ADPLL) [1] for Bluetooth radios has proven benefits of CMOS scaling and integration, demonstrators for more challenging wireless standards have emerged [2-6]. In the ADPLL, however, the digitally controlled oscillator (DCO) and time-to-digital converter (TDC) quantize the time and frequency tuning functions, respectively, which can lead to spurious tones and phase...
Recently, high-resolution TDCs have gained more and more popularity due to their increasing implementation in digital PLLs, ADCs, jitter measurement and time-of-flight measurement units. Similar to ADCs, existing architectures of TDCs can be divided into several categories: flash TDCs, pipeline TDCs, and SAR TDCs. The highest achievable time resolution of a TDC is mainly limited by the CMOS gate delay...
Buck regulators are widely employed in portable devices due to their high power-conversion efficiency. However, due to their spurious output noise, they are not directly used to power sensitive analog/RF modules, and subsequent linear low-dropout regulators (LDOs) are needed to generate secondary low-noise supply rails for these modules. This results in lower efficiency, and increased size and cost...
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