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Negative Bias Temperature Instability (NBTI) is a critical reliability issue and becoming more and more seriously in the modern CMOS technology. Many models have been proposed to account for the NBTI phenomena, but most of the models are based on the popular hydrogen reaction-diffusion (R-D) mechanisms. For the first time, in this work, a neutral interface-trap model due to the random variations of...
Wafer level reliability (WLR) issues of DRAM cell and peripheral transistors are discussed. Since the 70 nm technology node, recessed transistors have been accepted for assuring data retention time of DRAM cell transistors. Various recessed transistor structures suggest that the most important issue in reliability, in addition to optimizing data retention time, is the elimination of local regions...
In this work we present the integration of Band Engineered TANOS-like memories using HfSiON in the tunnel stack to boost the programming efficiency and improve cycling. An accurate correlation analysis between the gate-stack material physical properties and the memory performances is presented. In particular, the importance of the nitridation step of HfSiON on the memory retention characteristics...
In this paper, the reliability of the fluorinated hafnium oxide (HfO2) gate dielectric using novel and CMOS compatible fluorinated silicate glass (FSG) process has been studied comprehensively for the first time. Due to dangling bonds and oxygen vacancies recovery by the fluorine atoms, higher transconductance, smaller stress-induced threshold voltage and interface state degradation are therefore...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by...
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