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Multiobjective optimization taking area, power consumption and robustness into account was used to pick two implementations of the minority-3 function as building blocks to implement Muller C-elements. According to our simulations, the generally better among the two implementations was a 12 transistor implementation based on a 10 transistor minority-3 gate, when compared to a 24 transistor implementation...
Interconnects are becoming a major bottleneck in the design of modern Systems-on-Chip. Power consumption, propagation delay, statistical variability, and reliability are some of the key challenges that must be addressed to fully optimize the interconnect architecture. This work provides a thorough review and analysis of the advantages and possibilities of coding for addressing the aforementioned challenges...
A low power voltage management technique is proposed to reduce power consumption for domino circuits. Exploiting a rising and charge-sharing voltage allow the domino circuits to have both high performance and low power consumption. A test chip has been successfully validated to achieve 68% dynamic power consumption and 15% static power consumption respectively using TSMC 0.13um CMOS technology.
This paper presents design and analysis of D Flip-Flops (DFFs) using Carbon Nanotube Field-Effect Transistors (CNFETs). Two different DFF circuits are implemented. Circuit performance of CNFET models have been compared to silicon based CMOS models in terms of Clk-Q delay, average power, power delay product (PDP), setup time, hold time, minimum operating voltage, area and average leakage power. CNFET...
In this paper, detailed analysis is given on the design of metastable-hardened and soft-error tolerant flip-flops while maintaining the basic characteristics of low-power and high-performance. We also propose two new flip-flop designs: pre-discharge soft-error tolerant flip-flop (PDFF-SE) and sense-amplifier transmission-gate soft-error tolerant flip-flop (SATG-SE). Following our main design approach,...
Energy performance requirements are forcing designers of next-generation systems to explore approaches to least possible power consumption. Scaling of power supply voltage is major factor to reduce the power consumption. Threshold voltage may be reduced to achieve higher drive current and hence better speed, but at the cost of increase in the stand-by power. The technique to achieve ultra low power...
Low power device design is now a vital field of research due to increase in demand of portable devices. This research paper proposes the modified Single Edge Triggered (SET) D-flip flop design for the portable applications. Design is tested for various substrate bias voltages in sub-threshold region to opt for better design. Design comparison between previously reported design and modified design...
Increasing demand of portable devices creating larger scope in the field of Low power device design. VLSI designing of the efficient circuits is aiming towards the devices consuming less power and produces less delay with capability to operate in wider range of frequencies. This research paper proposes the modified Single Edge Triggered (SET) D-flip flop design for the low power applications. The...
Exploiting a charge sharing method enables a performance power management design for domino circuits. The domino circuits have both high performance and low power consumption. A test chip has been successfully validated using TSMC 0.13um CMOS technology. Reductions in dynamic power consumption of 68% and static power consumption of 15% are achieved.
Sub-threshold operation has been proved to be successful to achieve minimum energy consumption. It is well known that the sub-threshold device sizing is different from super-threshold due to different current behavior. The previously reported sub-threshold sizing methods assume that the current is proportional to the transistor width. However, we have found that the inverse narrow width effect has...
Multiple Supply Voltage (MSV) assignment has emerged as an appealing technique in low power IC design, due to its flexibility in balancing power and performance. However, clock skew scheduling, which has great impact on criticality of combinational paths in sequential circuit, has not been explored in the merit of MSV assignment. In this paper, we propose a discrete voltage assignment algorithm for...
In this paper, an ultra low power and low jitter 12bit CMOS digitally controlled oscillator (DCO) design is presented. Based on a ring oscillator implemented with low power Schmitt trigger based inverters. Simulation of the proposed DCO using 32nm CMOS Predictive Transistor Model (PTM) achieves controllable frequency range of 550MHz~830MHz with a wide linearity and high resolution. Monte Carlo simulation...
As the portable electronic products have being used extensively, many complex logic and mathematic functions need to be operated at low supply voltage for low power requirement. Different function blocks may need different supply voltages based on the performance requirements. With the emphasis on the efficiency in the transistor level, a novel level shifter is proposed. The proposed designs embedded...
In this paper, we propose addressing schemes to optimize Area Power Timing (APT) product, utilizing data dependency in Majority Based Full Adder (MBFA) topologies. With advancement in technology and demand of portability in applications, all the design parameters of a digital design viz. Area Power and Timing requirement have become equally important. As all the three need to be as small as possible,...
We investigate the impact of level-1 cache (CL1) parameters, level-2 cache (CL2) parameters, and cache organizations on the power consumption and performance of multi-core systems. We simulate two 4-core architectures - both with private CL1s, but one with shared CL2 and the other one with private CL2s. Simulation results with MPEG4, H.264, matrix inversion, and DFT workloads show that reductions...
Side channel attacks (SCAs) exploit the fact that security IC physical implementation of a cryptographic algorithm can leak information of the secret key. One of the most important SCA is Differential Power Analysis (DPA), that uses the power consumption dependence with the data processed to reveal critical information. To protect security devices against this issue, differential logic styles with...
This paper presents a sub-mW all-digital signal component separator (SCS) with a novel branch mismatch compensation scheme for OFDM LINC transmitters, including a phase calculator and a digital-control phase shifter (DCPS) pair. This chip is manufactured in 90nm standard CMOS process with active area 0.06mm2. The DCPS can generate phase-modulated signal at IF 100MHz with 8-bit resolution and RMS error...
An improved negative level shifter with high speed and low power consumption is presented. To reduce the switching delay and power consumption, a boost circuit is designed and additional charging current paths are introduced in the improved level shifter. The circuit has been designed in 130nm triple-well standard CMOS technology with a nominal power supply VDD of 1.5V and a negative voltage of -4...
Scan shift power can be reduced by activating only a subset of scan cells in each shift cycle. In contrast to shift power reduction, the use of only a subset of scan cells to capture responses in a cycle may cause capture violations, thereby leading to fault coverage loss. In order to restore the original fault coverage, new test patterns must be generated, leading to higher test-data volume. In this...
In this paper, we study residue logarithmic numbers system and design pipelined arithmetic logic unit for Residue Logarithmic Numbers System in order to be used for module set {2n -1,2n ,2n +1} that leads to implementation of integrated circuits for the general module with high speed and security but low power consumption. In this design a combination of two Logarithmic Number System and Residue Numbers...
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