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NoC performance largely depends on the underlying deadlock-free and efficient routing algorithm. Selection strategies play a pivotal role in the effectiveness of the routing algorithm by selecting the final output channel when there is more than one possible output link returned by an adaptive routing. In this paper a novel selection strategy, LATEX, is proposed that can be used with any adaptive...
Block finite impulse response (FIR) digital filters have potential for high-speed and low-power realization through parallel processing. In this paper, we suggest an efficient implementation of block FIR filters using multiple constant multiplication (MCM) technique. Constant multiplication methods are widely used for reducing computational complexity of implementation of FIR filters. Sub-expression...
Packet scheduling algorithms are viewed as one of the key mechanisms for increasing the diversity order, robustness and effectiveness of a wireless multi-user communication systems. Traditional packet scheduling algorithms are designed to save energy at the Base-station(BS) in downlink by exploiting tradeoffs between spectral efficiency, delay and energy while at the same time meeting the QoS requirements...
A diagnosis technique based on delay testing has been developed to map the severity of process variation on each cell/interconnect delay. Given this information, we demonstrate a post-silicon tuning method on row voltage supplies (inside a chip) to restore the performance of failed chips. The method uses the performance map to set voltages by either pumping up the voltage on cells with worse delays...
Power consumption is a critical design issue in embedded systems. This paper presents a structural customization approach, targeting two basic design structures for a multiple choice function that is common in an embedded system: tree structure and chain structure. A theoretical comparison between these two structures is performed. We find that the chain structure has a lower area cost and offers...
Network-on-chip (NoC) is being proposed as a scalable and reusable communication platform for future embedded systems. The performance of NoC largely depends on the underlying deadlock-free and efficient routing algorithm. When the adaptive routing returns a set of acceptable output channels, then a selection strategy is used to select the output channel, therefore the selection strategy affects the...
Complex web applications are usually served by multi-tier web clusters. With the growing cost of energy, the importance of reducing power consumption in server systems is now well-known and has become a major research topic. However, most of previous works focused solely on homogeneous clusters. This paper addresses the challenge of power management in Heterogeneous Multi-tier Web Clusters. We apply...
Finding a syndrome is the significant part of decoding rank codes procedure. Using a weak self-orthogonal basis one can decrease its complexity. In this case the major part of complexity evaluation is approximated by N(log N)2. It is less than the complexity when using Karatsuba-Ofman algorithm only.
Since the inception of the load-balanced switch, its elegant scheduling with 100% throughput has attracted a substantial amount of research interest. In this paper, we further investigate the energy consumption issues in the load-balanced switch based on the rate region analysis. We propose a self-adapting sleeping algorithm, not only providing throughput guarantee, but also taking advantages of period...
The ever-increasing chip power dissipation in SoCs has imposed great challenges on today's circuit design. It has been shown that multiple threshold and supply voltages assignment (multi-Vth/Vdd) is an effective way to reduce power dissipation. However, most of the prior multi-Vth/Vdd optimizations are performed under deterministic conditions. With the increasing process variability that has significant...
Security devices are vulnerable to differential power analysis (DPA) that reveals the key by monitoring the power consumption of the circuits. In this paper, we present the first DPA attack against an FPGA implementation of the camellia encryption algorithm with all key sizes and evaluate the DPA resistance of the algorithm. The Camellia cryptographic algorithm involves several different key-dependent...
Due to the importance of power/ground network, lots of researches have been made on it. But they only focused on the minimal area of it. By discussion on the relation among Vdd, performance and power consumption, this paper proposes an optimal algorithm using GA and SLP method where area, performance and power consumption can be simultaneously evaluated. As a result, the power/ground network is designed...
Currently, commercially available standard-cell libraries are often unstructured set of cells, suitable for several optimization criteria: speed, power, leakage and area consumption. Exploiting a large number of items makes the synthesis process and the library maintenance quite demanding. By smartly selecting a reduced set of cells, such efforts can be reduced, without critically affecting performance...
In this paper, an E-D-search-based algorithm is proposed to minimize power consumption with resources operating at multiple voltages under the timing constraints. The inputs to the algorithm consist of a data flow graph (DFG) representation of a circuit, the timing constraints, and a design library with fully characterized resources. Experimental results with a number of DSP benchmarks show that the...
In this paper we propose two advanced algorithms which allow for both differentiated quality-of-service (QOS) and power conservation in input-queued packet switches. These algorithms are based on two core ideas: first, we assume that the switch can operate in a number of operational speed modes; a higher speed mode serves more packets per time slot at the cost of higher power consumption. Second,...
To enhance power efficiency of battery powered wireless access devices, the behaviors of the mobile stations (MS) working in the sleep mode operation in IEEE 802.16e was researched with a method of the Markov chain model. By exploring the relationship among traffic load, power consumption and delay, we present a cross-layer design-based algorithm to tune the initial sleep window according to the randomization...
Multiple supply voltage (MSV) is an effective method to optimize the chip power consumption. In MSV design, the voltage island is a crucial concern that the blocks with the same voltage level are clustered into one or more voltage islands to reduce the costs of voltage supply network and level converter. The distribution of voltage islands depends on not only the feasible voltage assignment based...
Power consumption is a critical design issue in embedded processor design. One of common components in the processor is the Arithmetic and Logic Unit (ALU). Usually, ALUs are designed with a combinational logic circuit containing a number of functional components for different arithmetic and logic operations. An ALU can be constructed with a tree or a chain structure. Existing approaches to reduce...
The increasing viability of three dimensional (3D) silicon integration technology has opened new opportunities for chip design innovations, including the prospect of extending emerging systems-on-chip (SoC) design paradigms based on networks-on-chip (NoC) interconnection architectures to 3D chip designs. In this paper, we consider the problem of designing application-specific 3D-NoC architectures...
In this paper, we propose a dynamic traffic load-aware sleep mode operation to improve the power efficiency of battery powered IEEE 802.16e devices. By analyzing the sleep mode operation with a Markov chain model, we explore the relationship among traffic load, power consumption and idle check time. Based on the analytical results, we propose a dynamic algorithm to tune the idle check time according...
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