The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
To draw an accurate relationship between power dissipation and speed is a challenging problem in operational Amplifier with switch capacitance. However, transformation of current steer circuit into charge steer is an efficient technique to reduce power dissipation even at higher speed. In this paper, an efficient model is proposed to estimate the 1st and 2nd stage operational Amplifier's power dissipation...
In return for increased operating frequency and reduced supply voltage in nano-scale designs, their vulnerability to IR-drop-induced yield loss grew increasingly apparent. Therefore, it is necessary to consider delay increase effect due to IR-drop during at-speed scan testing. However, it consumes significant amounts of time for precise IR-drop analysis. This paper addresses this issue with a novel...
This paper proposes a novel scheme to manage capture power in a pinpoint manner for achieving guaranteed capture power safety, improved small-delay test capability, and minimal test cost impact in at-speed scan test generation. First, switching activity around each long path sensitized by a test vector is checked to characterize it as hot (with excessively-high switching activity), warm (with normal/functional...
Scan based at-speed testing has become mandatory in industry to detect delay defects today in order to maintain test quality and reduce test cost. However, the effects of power supply droop during test application often introduce timing uncertainty, such as clock stretch and additional gate delay. It leads to false failure and test escape during test and makes the application of the at-speed scan...
Instead of applying physical techniques to prevent crosstalk on off-chip parallel data buses, another approach is to code the sent information, [1]. Through developing of a crosstalk avoidance code (CAC) is possible to create a forbidden transition channel (FTC) that prevents transitions responsible for generating crosstalk, [2]. Rules used in developing a CAC can be very complex, and because of that...
To properly operate closed industrial control networks, it is required that communication with nearly constant delay bounds be supported. In [9] the authors introduced FlexTDMA in order to provide this support, and with minimal delay-jitter in an asynchronous network, under unicast communication. In this paper we consider how periodic on-off traffic and frame loss are managed in the presence of network...
In a circuit with enhanced-scan, any two-pattern test can be applied to detect delay faults. However, the tests may deviate substantially from functional operation conditions, and result in overtesting. Functional broadside tests create functional operation conditions during their functional clock cycles by using reachable states as scan-in states. To maintain a proximity to functional operation conditions...
We propose a Multi-Vdd Fine-Grained VariablePipeline (MVFG-VP) router in order to reduce power consumptionof Network-on-Chips (NoCs) designed for many-coreprocessors. MVFG-VP router adjusts its pipeline depth (i.e., communication latency) and supply voltage level of each inputand output channel independently. Unlike Dynamic Voltageand Frequency Scaling (DVFS) routers, MVFG-VP routersshare the same...
A 9-bit 100 MS/s flash-successive approximation register (SAR) analog-to-digital converter (ADC), which is suitable for wireless communication systems, is presented. To reduce the active area and power consumption, front-end track-and-hold circuits in the flash ADCs are substituted by dynamic ones. A variable delay loop for enhancing dynamic performances is also included in the ADC. The prototype...
This paper describes improvements to the technique of velocity selective recording (VSR) in which multiple neural signals are matched and summed to identify excited axon populations in terms of velocity. The signals are acquired using a multi-electrode cuff (MEC) which is now available as a component for use in implantable neuroprostheses. The improvements outlined in the paper involve the replacement...
This paper describes implementation issues for high speed 2-step-flash analog-to-digital converters (ADCs) without digital correction. A novel implementation for a multiplying digital-to-analog converter (MDAC) is described, which is a sample-and-hold amplifier, which includes a DAC, residue amplification and correlated double sampling (CDS), thereby omitting two-phase compensation differences. No...
A Hierarchical Torus Network (HTN) is a 2D-torus network of multiple basic modules, in which the basic modules are 3D-torus networks that are hierarchically interconnected for higher-level networks. Three deadlock-free adaptive routing algorithms called link-selection, channel-selection, and a combination of link-selection and channel-selection was proposed for the efficient use of physical links...
A 12-bit 60 MS/s SHA-less opamp sharing pipeline ADC utilizing switch-embedded dual-input current-reused opamp is presented in this paper. The proposed opamp sharing technique reduces the power consumption without suffering from memory effect. Two-phase overlapping clocks are proposed to ensure analog transistors in the common-mode feedback (CMFB) loop to always work in saturation thus avoiding common...
Discontinuous-conduction mode (DCM) operation is usually employed in DC-DC converters for small inductor on printed circuit board (PCB) and high efficiency at light load. However, it is normally difficult for synchronous converter to realize the DCM operation, especially in high frequency applications, which requires a high speed and high precision comparator to detect the zero crossing point at cost...
AMD's 4+ GHz x86–64 core codenamed “Piledriver” employs resonant clocking [1–4] to reduce clock distribution power up to 24% while maintaining a low clock-skew target. To support testability and robust operation at the wide range of operating frequencies required of a commercial processor, the clock system operates in two modes: direct-drive (cclk) and resonant (rclk). Leveraging favorable factors...
Continuous-Time ΔΣ Modulators are a popular architecture choice for ADCs in deep-submicron processes [1–4]. The maximum sampling rate is set by Excess Loop Delay (ELD) considerations. ELD comprises the comparator latency, feedback DAC delay (DEM delay etc.) and any additional delay due to parasitics. For a wideband 1b modulator clocking at high speeds (multi-GHz), the key challenge is modulator stability...
When applied over asymmetrical or potentially asymmetrical channels (unequal channel propagation times in the transmitting and receiving directions), such as commercial-class SDH/SONET networks, line current differential schemes need an external time reference for current data alignment if the sensitivity of the differential scheme is to be preserved. Modern line differential schemes can handle a...
We abstract the I/O functionality of continuous-time dynamical systems (e.g., SPICE netlists with combinational and sequential logic) as Finite State Machines (FSMs). This enables efficient simulation of large designs implemented with less-than-perfect devices and components, and also opens the door to formal verification of transistor-level designs against higher-level specifications. In particular,...
We propose a circuit switching Network-on-chip with a parallel probe searching setup method, which can search the entire network in constant time, only dependent on the network size but independent of the network load. Under a specific search policy, the setup procedure is guaranteed to terminate in time 3D+6 cycles, where D is the geometric distance between source and destination. If a path can be...
Power management in system-on-chip (SoC) has become one of the most crucial techniques for mobile devices. Among many intellectual properties (IPs) of SoC, a microprocessor, which is one of the major power consumers in the system, is a key component in SoC power management. Controlling idle states for microprocessors, which is typically implemented by combinations of clock gating and power gating,...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.