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To draw an accurate relationship between power dissipation and speed is a challenging problem in operational Amplifier with switch capacitance. However, transformation of current steer circuit into charge steer is an efficient technique to reduce power dissipation even at higher speed. In this paper, an efficient model is proposed to estimate the 1st and 2nd stage operational Amplifier's power dissipation...
As supply voltage is reduced, a power constrained test clock can be sped up in spite of the increased delay of the circuit. However, a large reduction in voltage makes the operation structurally constrained, requiring the clock to slow down. We determine an optimum supply voltage that allows fastest clock speed for a given power limit. Examples show that the test time can be reduced by as much as...
This paper investigates the effectiveness of a multi-voltage clock network design that is built using the mesh topology. Unlike a clock tree, a single clock mesh that spans multiple voltage domains is infeasible due to the incompatibility of voltage levels of the clock drivers on the electrically-shorted mesh — each voltage domain requires a separate mesh. These disjoint meshes need to be matched...
Because of the ever increasing number of cores present on a single chip, fast and energy efficient, inter-core data communication has become a major concern. Various networkon-chip (NoC) topologies and flow controls have been presented in literature. In this paper, for the first time, the benefits of a hierarchical heterogeneous NoC are quantized using a comprehensive circuit-interconnect technology...
Parameter variations in nanometer process technology are one of the major design challenges. They cause to be increased delay on the critical path and to change the logic level of internal nodes. The basic concept to solve these problems at the circuit level, design-for-variability (DFV), is to add error handling circuits at the conventional circuits so that they are robust to nanometer related variations...
The advent of dynamic CMOS logic, more precisely domino logic, made them widely used for the implementation of low power VLSI circuits. However, the main drawback of this logic is the non implementation of inverted logic. To implement the inverted logic, it is required to duplicate the logic circuit up to that part with inverted inputs. This obviously results the increase in area, delay as well as...
In this paper, we compared various different techniques of previously published Single Edge Triggered Flip Flops (SET FFs). Flip Flops are most essential elements in the design of sequential circuits. We did the comparison for their performance and power dissipation and have also compared the transistor count of each Flip Flop.
A low power Delay Locked Loop based Clock and Data Recovery circuit has been designed in this paper. A standby filter is a novel feature in this design. Level tracking technique is used for data recovery. The circuit is designed using Verilog HDL. The layout of the circuit is generated and verified using Cadence SoC Encounter. Total die area and total dynamic power dissipation of the circuit is 0...
The paper proposes a new methodology for optimization and characterization of flip-flops that can be utilized in designing EDA tool for NOC. In automated RTL to GDS II design space there is requirement of libraries with large number of cells. Now each design can have large number of different driving strength cells. Hence the paper proposes a methodology by virtue of which the library size can be...
The paper presents a new design for implementing a static Master-Slave Flip-flop with reduced transistor count for low power and high performance applications. The proposed flip-flop is realized using only eleven transistors (including an inverter to produce complementary clock signals locally) hence reducing the manufacturing cost. SPICE simulation results at a frequency of 250 MHz using 180 nm/1...
This paper presents some power results of Joint Photographic Experts Group (JPEG) in Field-Programmable Gate Array (FPGA) and provides some analysis and results in reduced dynamics-power methods of it. The dynamic power consumed by a digital CMOS circuit is directly proportional to both switching activity and payload capacitance. We use Xilinx XPower Analyzer to analyze the impact of different switching...
GHz-range applications that operate in a variety of signal situations and/or multiple standards require highly programmable responses that cannot be provided by analog circuits. Conventional digital solutions suffer from aliasing, thus requiring a complicated antialiasing filter and/or extremely high clock speeds with high power dissipation. An alternative is continuous-time (CT) DSP [1], which uses...
In this paper, MOS current mode logic (MCML) and dynamic current mode logic (DyCML) techniques are analyzed and applied to the generation of digital arithmetic circuits. A full adder structure is demonstrated, analyzed and compared with equivalent CMOS, Domino and CPL structures and realized using 0.18 μm CMOS technology operating with 1.5 V and -1.5 V supply voltages. Also, a four bit multiplier...
Sometimes reducing the power dissipation of resource constrained electronic systems, such as those built for deep-space probes or for wearable devices is a top priority. In signal processing, it is possible to have an acceptable quality of the signal even introducing some errors. In this work, we analyze two methods to degrade the precision of arithmetic operations in DSP to save power. The first...
This paper presents the design of a low-power multi-channel time-based analog-to-digital converter (ADC) for the instruments dedicated to high-energy physic experiments and biomedical imaging applications. The proposed ADC is realized by using two-step conversion scheme: the voltage-to-time conversion (VTC) and the digital-to-time conversion (TDC). In VTC, the classic Wilkinson-type architecture are...
Low-power devices are indispensable for modern electronic applications, and numerous hardware/software techniques have been developed for drastically reducing functional power dissipation. However, the testing of such low-power devices has increasingly become a serious problem, especially in at-speed scan testing where a transition is launched at the output of a flip-flop and the corresponding circuit...
The paper introduces a new low power, high density double edge triggered, (DET) flip-flop. The proposed DET flip-flop is implemented using lesser number of transistors as compared to other state of the art double edge triggered flip-flops designs. Simulation at 250MHz frequency using 180nm/1.8V CMOS technology with BSIM 3v3 parameters, the proposed design shows an improvement of upto 58.63%, 55.7%...
In ASICs with structure sizes of 65nm and below the requirements of precise and robust clock networks continuously increase. High-speed circuits already use full-custom clock-meshes instead of buffer trees. Recently new clock-mesh synthesis tools with more automation have become available which better suit ASIC design flows. This paper provides a QoR analysis of these meshes versus highly optimized...
This paper reviews research in event-driven data acquisition and associated digital signal processing. The approaches considered can potentially offer significant energy and bandwidth savings with certain important classes of signals, in which activity varies significantly with time. An extensive bibliography is provided.
This paper presents a novel digital delay-locked loop (DDLL) dedicated to generate multiphase delayed clocks for the development of the multi-channel analog-to-digital converters (ADCs) and/or time-to-digital converters (TDCs). The DDLL consists of a digital delay chain using linear delay elements, a Bangbang phase detector, a Up/Down counter and a digital filter. The digital filter is utilized to...
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