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As compared to static logic, domino logic circuits are always preferable for high performance circuit designs because of their less number of transistor requirement and high operational speed. Due to the presence of charge sharing problem and less noise tolerance this logic is not broadly accepted for all logic designs. The desired output of the circuit can change with a little noise pulse in the...
Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS...
This paper proposes an algorithm to construct an X-clock tree with double via insertion that connects several voltage islands for power minimization. We first construct the X-clock tree for each voltage island and make double via insertion for this tree to improve yield and reliability. Then we combine these X-clock trees based on a well-defined connection with inserted level shifters to reduce power...
Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS...
In this paper, we present an adaptive voltage scaling (AVS) scheme to tune the supply voltage of digital circuits according to variations. Compared to worst-case designs, which produce fixed and excessively large safety margins, a considerable amount of energy can be saved by this approach. The AVS technique is based on in-situ delay monitoring, i.e. observing the timing in critical paths. For this...
In order to minimize the size and improve the efficiency of power consumption, most of wireless implantable Microsystems use Amplitude Shift Keying (ASK) modulator to transmit, through a RF link, data and energy to the internal implants. In this paper, we propose a new structure of wireless data and clock recovery dedicated for biomedical implants. It consists in a fully integrated ASK demodulator...
A novel energy efficient, Single Event Upset (SEU)/Single Event Transient (SET) tolerant Flip-Flop (FF) design is proposed which is suitable for ultra-low power systems that operate between sub-threshold (250mV) and super-threshold (1.0V) supply voltages. In comparison to an existing sense-amplifier based radhard FF, the proposed FF provides equivalent SEU/SET resilience at super-threshold voltage...
This paper discusses about the design and implementation of low power automatic scheduled alarm system whose schedule and time can be programmed using a computer via Universal Serial Bus port. Educational institutions, Factories, hospitals, etc are some places where this can be primarily used. The system uses an 8 bit PIC18f4550 microcontroller, a DS12626 Sanyo 16×2 character LCD, a DS1208 Real Time...
Power consumption is a critical design issue in embedded systems. This paper presents a structural customization approach, targeting two basic design structures for a multiple choice function that is common in an embedded system: tree structure and chain structure. A theoretical comparison between these two structures is performed. We find that the chain structure has a lower area cost and offers...
A multiphase all-digital delay-locked loop (DLL) with reuse SAR has been designed with TSMC 0.18μm CMOS technology. The proposed reuse successive approximation register (Reuse SAR) reduces the hardware cost effectively as compared with a conventional SAR or a two-stage SAR. The digital to voltage convertor has six coarse controlled bits and six fine controlled bits to adjust voltage for voltage controlled...
Side channel attacks (SCAs) exploit the fact that security IC physical implementation of a cryptographic algorithm can leak information of the secret key. One of the most important SCA is Differential Power Analysis (DPA), that uses the power consumption dependence with the data processed to reveal critical information. To protect security devices against this issue, differential logic styles with...
In this paper the design and implementation of a delay-locked loop based temperature compensated MEMS clock is presented. The system is providing a temperature compensated 48 MHz clock signal for the range of - 40 to 85°C. The temperature compensation is achieved by a combination of initial and an autonomous background calibration. The main design guidelines have been on high integration level and...
A low-jitter 300- to 800-MHz de-skew clock generator for arbitrary wide range delay is proposed to minimize the instability of the clock settling while maintaining a wide loop bandwidth. The clock skew problem is detrimental in the high speed applications, especially when the skew is longer than multi-cycles. The proposed generator was fabricated in a 0.18-μm CMOS process. The clock generator...
This paper presents a new architecture for a DLL based frequency synthesizer for wireless transceivers. Owing to its DLL based nature, the synthesizer generates the target frequencies with minimum phase noise. The proposed architecture takes the advantage of a combination of a frequency divider and an edge combiner to create the desired frequencies. As an example, the synthesizer is adopted to create...
The paper introduces a new low power, high density double edge triggered, (DET) flip-flop. The proposed DET flip-flop is implemented using lesser number of transistors as compared to other state of the art double edge triggered flip-flops designs. Simulation at 250MHz frequency using 180nm/1.8V CMOS technology with BSIM 3v3 parameters, the proposed design shows an improvement of upto 58.63%, 55.7%...
In this paper a self-oscillating ΣΔ modulator is presented. By introducing this self-oscillation in the system, the loop filter operates at a speed significantly lower than dictated by the clock frequency. This allows for a simple and power efficient design of the opamps used in the loop filter. The self-oscillation is induced here by introducing a controlled delay in the feedback loop of the modulator...
Traditional architecture design approaches hide hardware uncertainties from the software stack through over-design, which is often expensive in terms of power consumption. The recently proposed quantitative alternative of stochastic computing requires circuits and processors to be correct only probabilistically and use less power. In this paper, we present the first step towards a theory of stochastic...
Low power is a challenging work in processor design. Implementing power optimization on all components of the processor is a choice. One of the most basic components in processor is the Arithmetic and Logic Unit (ALU), which performs arithmetic operations and logic operations. The architecture of ALU has several implications on power consumption, delay and area. In this paper, different ALU architectures...
The parameters of CMOS device will be affected by the variation of temperature and process variation. Due to these variations, a ring oscillator implemented in CMOS process will not have an constant output frequency which is designed in CAD tools. In order to get a constant frequency, additional circuit is needed to compensate the variation in both temperature and process. After investigate the drawback...
Resonant clocking is an emerging effective method for reducing power consumption in the clock distribution network. In this technique a resonant (sinusoidal) clock replaces the traditional square wave clock signal. In this paper we combine the emerging resonant clocking technique with the well known dual-edge triggering scheme to enable further power reduction in the clock tree. We propose dual-edge...
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