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We propose an asynchronous, decentralized algorithm for consensus optimization. The algorithm runs over a network of agents, where the agents perform local computation and communicate with neighbors. We design the algorithm so that the agents can compute and communicate independently at different times and for different durations. This reduces the waiting time for the slowest agent or longest communication...
Timing Optimization is one of the most important objectives of the designer in the Modern VLSI world. Memory elements play a vital role on Digital World. The basic memory elements of designer considerations are Latch and flip flop. In this paper, we analyze the design of Single-bit Flipflop (SBFF) and made performance comparison over the Multi-bit Flip-flop (MBFF). For improving Flip flop performance...
Deep sub micron designs are susceptible to huge variations, justifying the in-situ optimization of power consumption in SoCs and IPs. It is essential to scale voltage to the lowest possible value to get maximum power saving while ensuring correct operation. Accurate estimation of error rates is required to use recovery driven DVFS techniques such as slack optimization [1], [2]. Due to extra logic...
The testing, verification and evaluation of wireless systems is an important but challenging endeavor. The most realistic method to test a wireless system is a field deployment. Unfortunately, this is not only expensive but also time consuming. In this paper, we present the design and implementation of a digital wireless channel emulator, which connects directly to a number of radios, and mimics the...
With the increasing popularity of mobile and energy-limited devices, the trend in the field of microprocessor design has shifted from high performance to low power operation. A common low power technique is reducing the supply voltage during periods of low utilization. However, this is limited by the safety margins needed to protect the processor from infrequent voltage glitches and environmental...
Power reduction is nowadays becoming the first consideration in VLSI design. Low power is one of major concerns in deeply scaled CMOS technologies. There have been many methods in very wide rang to achieve this objective. And the Register-Transfer level (RTL) has become the most effective stage in low power VLSI design, according to the significant power optimization impact and accurate power estimation...
With increasing circuit complexities, design bugs are commonly found in late design stages, and thus engineering change orders (ECOs) have become an indispensable process in modern VLSI design. Most prior approaches to the timing ECO problem are concerned about combinational logic optimization. In contrast, this paper addresses the problem in the sequential domain to explore more optimization flexibility...
By assigning intentional clock arrival times to the sequential elements in a circuit, clock skew scheduling (CSS) techniques can be utilized to improve IC performance. Existing CSS solutions work in a conservative manner that guarantees “always correct” computation, and hence their effectiveness is greatly challenged by the ever-increasing process variation effects. By allowing infrequent timing errors...
The paper proposes a new methodology for optimization and characterization of flip-flops that can be utilized in designing EDA tool for NOC. In automated RTL to GDS II design space there is requirement of libraries with large number of cells. Now each design can have large number of different driving strength cells. Hence the paper proposes a methodology by virtue of which the library size can be...
The study in this paper is aimed at improving the performance of a network processor design (XDNP) based on a Virtex-4 FPGA by using the PlanAhead tool offered by XILINX. PlanAhead gives a unique visibility into the design. The tool can very quickly identify the critical path, and then supply hierarchical floorplanning to achieve faster timing closure. XDNP is targeted at networking applications requiring...
Design variability due to within-die and die-to-die variations has potential to significantly increase the maximum operating clock period and the leakage power of the system in future process technology generations. When minimizing total energy of an MPSoC system, the variations in both the clock period and the leakage power of the multiple cores have to be taken into account. This paper targets system...
Satisfying clock skew constraint is one of the most important tasks in the clock tree synthesis. Moreover, the task becomes much harder to solve as the clock tree is designed under multiple power mode environment, in which the voltage applied to some design module varies as the power mode changes. Recently, it is shown that adjustable delay buffer (ADB) whose delay can be tuned dynamically can be...
Electromagnetic Interference (EMI) generated by electronic systems is increasing with operating frequency and shrinking process technologies. The clock distribution network is one of the major causes of on-chip EMI. In this paper, we discuss the EMI problem in clock tree design. Spectrum analysis shows that slew rate of clock signal is the main parameter determining the high-frequency spectral content...
Clock skew scheduling is an effective technique to improve the performance of sequential circuits. However, with process variations, it becomes more difficult to implement a large number of clock delays in a precise manner. Multi-domain clock skew scheduling is one way to overcome this limitation. In this paper, we prove the NP-completeness of multi-domain clock scheduling problem, and design a practical...
Clock networks contribute a significant fraction of dynamic power and can be a limiting factor in high-performance CPUs and SoCs. The need for multi-objective optimization over a large parameter space and the increasing impact of process variation make clock network synthesis particularly challenging. In this work, we develop new modeling techniques and algorithms, as well as a methodology, for clock...
There is a growing demand for high-performance, low-power systems, particularly in portable devices. New approaches to design are needed in technologies with feature sizes of 90 nm and below to reduce leakage power and to deal with process variations, which force designers to use increasingly conservative delay estimations. This paper presents a variable clock generator for a conventionally-designed...
Driven by growing application requirements and accelerated by current trends in microprocessor design, the number of processor cores on modern supercomputers is increasing from generation to generation. However, load or communication imbalance prevents many codes from taking advantage of the available parallelism, as delays of single processes may spread wait states across the entire machine. Moreover,...
Digital signal processing in continuous-time can result in a number of advantages compared to classical sampled data systems, while the inherent advantages of digital implementations with respect to programmability and noise immunity are retained. A main difference to sampled data systems is the realization of the delay elements which are implemented as quasi-continuous time delay lines. In this paper...
Clock meshes are an important resource for high performance circuit designers due to its robustness to variability. Until recently, there were no tools able to support the use of clock meshes in automated synthesis flows. In the last years commercial tools were adapted to support clock meshes and the academia has addressed the problems of clock mesh design automation and optimization. However, current...
This article concerns the hardware iterative decoder for a subclass of LDPC (Low-Density Parity-Check) codes that are implementation oriented. They are known as Architecture Aware LDPC (AA-LDPC). The decoder has been implemented in a form of parameterizable VHDL description. To achieve high clock frequency of the decoder hardware implementation, a large number of pipeline registers has been used in...
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