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Analog Comparator is designed to compare two analog inputs and outputs a logical signal indicating which of the inputs is greater or lesser. Comparators, being an essential building block of most high speed devices like Analogue to Digital Converters, are one of the most important components used in signal processing and communication systems. Also it plays a challenging role in high speed mixed signal...
Timing Optimization is one of the most important objectives of the designer in the Modern VLSI world. Memory elements play a vital role on Digital World. The basic memory elements of designer considerations are Latch and flip flop. In this paper, we analyze the design of Single-bit Flipflop (SBFF) and made performance comparison over the Multi-bit Flip-flop (MBFF). For improving Flip flop performance...
Deep sub micron designs are susceptible to huge variations, justifying the in-situ optimization of power consumption in SoCs and IPs. It is essential to scale voltage to the lowest possible value to get maximum power saving while ensuring correct operation. Accurate estimation of error rates is required to use recovery driven DVFS techniques such as slack optimization [1], [2]. Due to extra logic...
Design methodologies such as Razor [3,4] minimize power dissipation by slowing down circuits so as to eliminate timing slacks to the point where occasional timing errors are observed. The main challenge here is the design of efficient mechanisms to detect and recover from these infrequent errors without loss of functionality. We present a design for widely used Wallace multipliers where, because of...
With the increasing popularity of mobile and energy-limited devices, the trend in the field of microprocessor design has shifted from high performance to low power operation. A common low power technique is reducing the supply voltage during periods of low utilization. However, this is limited by the safety margins needed to protect the processor from infrequent voltage glitches and environmental...
This paper presents a construction of dual-edge-triggered flip-flops (DET-FFs) with timing error detection capability. The proposed FF is based on a conventional DET-FF and a conventional timing error detection method. While the conventional timing error detection uses a transition detector with the area of large, the proposed FF uses internal signals in a DET-FF as an alternative of the transition...
Due to continuous technology scaling, the nodal capacitances reduction and power supply voltage lowering result in an ever decreasing minimal charge capable of upsetting the logic state of memory circuits. CMOS circuits operating under sub-threshold voltage region are more susceptible than ever to externally induced radiation that is likely to bring about the occurrence of soft errors. Therefore,...
In the presence of process variation, conventional worst-case timing analysis is no longer able to fully realize the benefit of scaling and integrating. As a result, statistical static timing analysis (SSTA) is essentially needed in high-level synthesis (HLS) stage. This paper presents the first work to develop a design framework of SSTA for HLS based on transparent latches. An integer linear programming-based...
This paper presents a soft error hardened latch suitable for reliable operation. The proposed circuit is aimed to tackle the particle hit effect on the internal nodes, external logic, as well as the pulse generator circuit. The hardening method is based on redundancy to protect internal nodes and filter out transients resulted from combinational logic. It also uses redundant clocking technique which...
This paper presents a low-power dynamic comparator utilizing a novel time-domain bulk-driven offset cancellation scheme with minimal additional power consumption and delay. It uses an open loop dynamic phase detector to achieve very high precision. The circuit is designed in a 0.6-µm process. The simulation results show that the circuit consumes 540 nA current at 100 kHz clock frequency and the proposed...
With CMOS technology shrinking to nanoscale regime, the susceptibility of a single chip to soft errors increases. Hence, the critical charge (Qcrit) of circuit decreases and this decrease is expected to continue with further technology scaling. In this paper previous hardened latch circuits are analyzed and it is found that previous designs offer limited protection against soft error especially for...
Parameter variations in nanometer process technology are one of the major design challenges. They cause to be increased delay on the critical path and to change the logic level of internal nodes. The basic concept to solve these problems at the circuit level, design-for-variability (DFV), is to add error handling circuits at the conventional circuits so that they are robust to nanometer related variations...
Power is often cited as a key design metric for IC designs. However, for many integrated solutions a better measure of design quality is the overall energy efficiency of the design as low power does not always imply high energy efficiency. Many design tradeoffs must be made to balance the often-conflicting goals of high performance, low power, small area and high efficiency. This paper will use the...
It is well known that circuits fail when one or more of the constituent components fails, due -for example- to phenomena such as electromigration in wires. Such hard failures, typically due to topological changes in circuit connectivity, are treated distinctly from soft failures which could be due to components drifting out of spec over time. However, in certain types of circuits, such as memory,...
As process technology continues to shrink, Negative Bias Temperature Instability (NBTI) has become a major reliability issue in CMOS circuits. NBTI degrades the threshold voltage of the PMOS transistor and, over time, causes the operating speed of the circuit to become slower (also known as the aging effect). In this paper, we introduce a new aging-aware Flip-Flop (FF) that is based on accurate, run-time...
A high-speed dual-phase domino circuit design with high performance and reliable characteristics is proposed. The cell-based automatic synthesis flow supports the quick design of high performance chips. The test chip of a dual-phase 64-bit high-speed multiplier with a built-in performance adjustment mechanism has been successfully validated using TSMC 0.18um CMOS technology. The test chip shows a...
Flip-flops (FFs) are key building blocks in the design of high-speed energy-efficient microprocessors, as their data-to-output delay (D-Q) and power dissipation strongly affect the processor's clock period and overall power [1]. From previous analyses [2], the Transmission-Gate Pulsed Latch (TGPL) [3] proved to be the most energy-efficient FF in a large portion of the design space, ranging from high...
Continuous-Time ΔΣ Modulators are a popular architecture choice for ADCs in deep-submicron processes [1–4]. The maximum sampling rate is set by Excess Loop Delay (ELD) considerations. ELD comprises the comparator latency, feedback DAC delay (DEM delay etc.) and any additional delay due to parasitics. For a wideband 1b modulator clocking at high speeds (multi-GHz), the key challenge is modulator stability...
Several methods that eliminate timing margins by detecting and correcting transient delay errors have been proposed [1–5]. These Razor-style systems replace critical flip-flops with ones that detect late arriving signals, and use architectural replay to correct errors. However, none of these methods have been applied to a complete commercial processor due to their architectural invasiveness. In addition,...
The Razor dynamic voltage scaling approach uses in situ error-detection and correction of timing errors to reclaim safety margins for improved energy-efficiency in digital circuits. In this paper, we propose the use of a time borrowing window on critical logic paths, over which timing errors can resolve safely without an explicit replay mechanism. We demonstrate that time borrowing can be incorporated...
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