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Comparators are a critical element of Analog-to-Digital converters (ADCs) intended to operate in a harsh environments such as the automotive. The influence of temperature on key comparator properties such as the delay must be well understood to maximize their speed. In this paper a Double-Tail latch analysis leads to an analytical expression for the delay to more accurately guide the design over a...
In designing synchronous circuits and memory elements, Flip-flops (FF) play an integral role. In the present era, the demand of area efficient, lesser delay, and faster devices are the major concern. This paper present the comparative study of Flip Flops in terms of area and delay. The problem of device size is very dominant today because the demand for small device size along with lesser number of...
We propose an asynchronous, decentralized algorithm for consensus optimization. The algorithm runs over a network of agents, where the agents perform local computation and communicate with neighbors. We design the algorithm so that the agents can compute and communicate independently at different times and for different durations. This reduces the waiting time for the slowest agent or longest communication...
For 7 series Xilinx FPGAs, this paper shows that it is risky to believe that so fundamental operation as data delay must be always implemented without wasting chip area, even when design tools are not especially guided by a developer. Against this background, two solutions are presented that allow for minimizing the area occupied by flip-flops used to delay data that comes from outside the slices...
Analog Comparator is designed to compare two analog inputs and outputs a logical signal indicating which of the inputs is greater or lesser. Comparators, being an essential building block of most high speed devices like Analogue to Digital Converters, are one of the most important components used in signal processing and communication systems. Also it plays a challenging role in high speed mixed signal...
As compared to static logic, domino logic circuits are always preferable for high performance circuit designs because of their less number of transistor requirement and high operational speed. Due to the presence of charge sharing problem and less noise tolerance this logic is not broadly accepted for all logic designs. The desired output of the circuit can change with a little noise pulse in the...
This paper proposes a Low-Power, Energy Efficient 4bit Binary Coded Decimal (BCD) adder design where the conventional 4-bit BCD adder has been modified with the Clock Gated Power Gating Technique. Moreover, the concept of DVT (Dual-vth) scheme has been introduced while designing the full adder blocks to reduce the Leakage Power, as well as, to maintain the overall performance of the entire circuit...
At-speed delay testing is inevitable for improving the test quality of modern high-speed semiconductor chips. This paper presents a scan cell architecture for at-speed testing of delay faults in inter-clock logic. The technique utilizes commercially available ATPG tools for test pattern generation and internal PLL clocks for test pattern application. The hardware modification is contained within the...
Increasing demand of portable devices creating larger scope in the field of Low power device design. VLSI designing of the efficient circuits is aiming towards the devices consuming less power and produces less delay with capability to operate in wider range of frequencies. This research paper proposes the modified Single Edge Triggered (SET) D-flip flop design for the low power applications. The...
Packet-based methods for transporting timing information are becoming increasingly important as networks shift from circuit-switched to packet-switched architectures. The packet-delay variation inherent in packet networks is a primary source of clock noise. This paper addresses suitable methods for analyzing Packet Delay Variation (PDV) and the impact on synchronization. Metrics appropriate for analysis...
As technology scales, resistive defects, particularly via voids, are becoming an increasing problem. While such defects may only cause a small timing increase along some signal paths during test, they often grow and lead to early life failures in the field. Testing for small delay defects is therefore receiving considerable attention in recent years because the traditional burn-in approach to screen...
Faster than at-speed testing provides an effective way to detect small delay defects (SDDs). It requires test patterns to be delicately classified into groups according to the delay of sensitized paths. Each group of patterns is applied at certain frequency. In this paper, we propose to generate tests for faster than at-speed testing using path delay fault (PDF) model and single path sensitization...
This paper presents a design for an on-chip high-speed clocked-comparator for high frequency signal digitization. The comparator consists of two stages, amplification and regenerative, comprising a total of 10 MOS transistors. The design is implemented in 65nm CMOS technology. Also, the paper presents a new cost effective technique for measuring the maximum speed of the clocked comparator. The measurement...
We present the first sensor network architecture to monitor integrated circuits (IC) thermal and energy activity. The sensor network consists of a set of simple gates, which are superimposed over the actual design of any IC. The sensing network and the actual IC design are completely disjoint in order to enable their simultaneous operation. Since the delay of gates is proportional to their temperature,...
The unstable/unpredictable LSI operation caused by the PVT (Process Voltage Parameter) variations, along with the aging effect such as NBTI/PBTI, is one of the serious issues in current and future scaled LSIs. In these situations, where operation environments in the field are hard to predict at the stages of circuit design and test, the conventional approach of the margin-based design and test in...
ICx Radiation, Inc. has implemented a novel timing method for use in a Compton telescope that is capable of nanosecond timing resolution. A critical task in Compton telescope design is to minimize the timing variance between detectors in a large array in order to reduce the background. The voxelSPEC has been developed to combine precise timing with pulse processing electronics in a single device,...
Benefit from wave union, the bins (especially the ultra-wide bins) are sub-divided by each other, making FPGA TDC achieve a resolution beyond its cell delay. At such high level resolution, delay chain becomes very sensitive to the environment disturbance, including power supply voltage, temperature and current surge. On chip calibration needs lots of events and hence cannot follow fast delay changes...
Synchronization interfaces in a network-on-chip (NoC) are becoming vulnerable points that need to be safeguarded against link delay variations and signal misalignments. This paper addresses the challenge of designing a process variation and layout mismatch tolerant link for GALS NoCs by implementing a self-calibration mechanism. A variation detector senses the variability-induced misalignment between...
AFDX (Avionics Full Duplex Switched Ethernet) standardized as ARINC 664 is a major upgrade for avionics systems. But guarantees on upper bounds of end-to-end communication delays are required for certification purposes. The objective of this paper is to present an improved modeling approach using timed automata for calculation of exact worst case delays. This approach takes advantage of local scheduling...
A new loop filter design for third-order charge-pump phase locked loops is presented. The design is based on a discrete-time model with loop delay. In addition to the closed-loop stability, this method deals with the practical considerations: ripple swing, reference spur, and stability margin. Some of which are derived in terms of linear matrix inequalities (LMIs). Trade-off among the conflicting...
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