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In the modern era of electronics and communication decoding and encoding of any data(s) using VLSI technology requires low power, less area and high speed constrains. The viterbi decoder using survivor path with necessary parameters for wireless communication is an attempt to reduce the power and cost and at the same time increase the speed compared to normal decoder. This paper presents three objectives...
For the design of real-time embedded systems, analysis of performance and resource utilization at an early stage is crucial to evaluate design choices. Network Calculus and its variants provide the tools to perform such analyses for distributed systems processing streams of tasks, based on a max-plus algebra. However, the underlying model employed in Network Calculus cannot capture correlations between...
A comma detection and word alignment circuit is proposed for a 6.25-Gb/s SerDes. In order to achieve a high speed, a new architecture of combined parallel and pipelined is employed. Based on the proposed structure, a high speed comma detector is implemented using 0.18im CMOS technology. Post simulation result indicates that the circuit can operates up to 770MHz with a power consumption of 10.8 mW...
In order to improve anti-jamming capability, the tactical data link uses RS (31, 15) coding/decoding in data transmission. In this paper, a RS (31, 15) hardware decoder base on RIBM algorithm is introduced, and this decoder is designed and implemented by pipeline algorithm. To make up the key equation module's deficient in the whole pipeline, a modified RIBM algorithm is proposed, and the logic resource...
A phase-based delta-sigma analog-to-digital converter (ADC) architecture with a combination voltage-controlled and digitally-controlled delay lines (VCDL-DCDL) is presented. The architecture uses this VCDL-DCDL combination as the phase-domain counterparts of an ADC-DAC in a traditional delta-sigma modulator. Simulation results of the new modulator achieve a 60.1 dB SNR, or a 9.7 bit over a 10 MHz...
In order to minimize the size and improve the efficiency of power consumption, most of wireless implantable Microsystems use Amplitude Shift Keying (ASK) modulator to transmit, through a RF link, data and energy to the internal implants. In this paper, we propose a new structure of wireless data and clock recovery dedicated for biomedical implants. It consists in a fully integrated ASK demodulator...
We present an energy-reduction strategy for applications which are resilient, i. e. can tolerate occasional errors, based on an adaptive voltage control. The voltage is lowered, possibly beyond the safe-operation region, as long as no errors are observed, and raised again when the severity of the detected errors exceeds a threshold. Due to the resilient nature of the applications, lightweight error...
A novel implementation of the N-bit Successive Approximation Register (SAR) Delay Locked Loop (DLL) is proposed with a significantly reduced hardware overhead relative to the conventional approach. The hardware overhead for the proposed 2-bit SAR scheme is only 25% of that for the conventional 2-bit SAR scheme. In this work, a complete All-Digital DLL (ADDLL) design implementing the proposed 2-bit...
Multi-core processing is a growing industry trend as single core processors rapidly reach the physical limits of possible complexity and speed. In case of single core processors, the increased performance incurs the more heating and cooling arrangements, as heating is a consequence of power dissipation. The cache design in existing SMT and superscalar processors is optimized for latency, but not for...
This article concerns the hardware iterative decoder for a subclass of LDPC (Low-Density Parity-Check) codes that are implementation oriented. They are known as Architecture Aware LDPC (AA-LDPC). The decoder has been implemented in a form of parameterizable VHDL description. To achieve high clock frequency of the decoder hardware implementation, a large number of pipeline registers has been used in...
The mapping of high level applications onto the coarse grained reconfigurable architectures (CGRA) are usually performed manually by using graphical tools or when automatic compilation is used, some restrictions are imposed to the high level code. Since high level applications do not contain parallelism explicitly, mapping the application directly to CGRA is very difficult. In this paper, we present...
In a flash ADC, output of the comparators constitute the thermometer code. This thermometer code is converted to binary code with the help of a thermometer to binary decoder using a ROM. However, this conversion scheme suffers from metastability and bubble errors. A novel ROM architecture has been proposed which suppresses metastability, both first and second order bubble errors. It eliminates the...
As the microprocessor speed increases from 500MHz to 1GHz and beyond, SOC designers are forced to innovate new schemes in their use of cache memory for high speed access. In this paper, clock to wordline path delay is optimized using a novel circuit design technique. Using this novel circuit, clock to word line path delay is optimized by 2.5 times at worst case corner. For a typical memory instance...
Several techniques have been presented in our previous work for lessening the delays for instruction decompression when branching occurs. However, their costs are still relatively high. In this paper, a new preprocessing-based technique is presented to reduce the cost and increase the performance. The synthesized results for several benchmarks show that the average saving of area is about 37.5%.
This paper describes the design and implementation of a hardware module to calculate the decimal floating-point (DFP) multiplication compliant with the current IEEE-754-2008 standard. The design proposed is made up of independent stages: IEEE-754 coder / decoder, decimal multiplier and rounding. The decimal multiplication is based on a previously designed BCD multiplier. The novelty is the design...
This paper proposes a full custom design of a 9-write and 17-read multi-port register file. The proposed register file can fulfill one read-after-write access in one system cycle with a synchronous read and an asynchronous write. The design employs a single-ended sense amplifier and a high-speed SCL address-decoder as write decoder controlled by VCLK, which is generated through a novel positive edge...
Low-power and high-throughput Viterbi decoder (VD) for tail-biting convolutional codes is presented in this paper. First, a low complexity radix-4 VD with enhanced decoding features such as end-state forcing and best-state trace back is presented. Second, simple pre-decoding is proposed to decrease the runtime of VD, resulting in significant power saving. The design is implemented in 0:9 V TI 45-nm...
Synchronous pipelines usually have a fixed clock frequency determined by the worst-case process-voltage-temperature (PVT) analysis of the most critical path. Higher operating frequencies are possible under typical PVT conditions, especially when the most critical path is not triggered. This paper introduces a design methodology that uses asynchronous design to generate the clock of a synchronous pipeline...
A Goldschmidt iterative divider for quantum-dot cellular automata (QCA) is designed using a new architecture that solves a problem that arises in implementing conventional state machines in QCA. State machines for QCA often have synchronization problems due to the long delays between the state machines and the units (i.e., the computational circuits) to be controlled. To resolve this problem, a data...
In order to acquire high speed switching in high-speed fiber channel switch network, a method named MRTF (the method of reducing the token's frequency) used to reduce the token's frequency is put up, and the corresponding switch is designed. In this method MRTF, the token is coded with RTFC, the token reducing-frequency code which is a special sequence of `0' and `1' , then it's frequency may be reduced...
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